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W78LE812 Datasheet(PDF) 18 Page - Winbond |
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W78LE812 Datasheet(HTML) 18 Page - Winbond |
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18 / 25 page ![]() W78LE812 - 18 - Data Read Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES ALE Low to RD Low TDAR 3 TCP - ∆ - 3 TCP + ∆ nS 1, 2 RD Low to Data Valid TDDA - - 4 TCP nS 1 Data Hold from RD High TDDH 0 - 2 TCP nS Data Float from RD High TDDZ 0 - 2 TCP nS RD Pulse Width TDRD 6 TCP - ∆ 6 TCP - nS 2 Notes: 1. Data memory access time is 8 TCP. 2. " ∆" (due to buffer driving delay and wire loading) is 20 nS. Data Write Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low TDAW 3 TCP - ∆ - 3 TCP + ∆ nS Data Valid to WR Low TDAD 1 TCP - ∆ - - nS Data Hold from WR High TDWD 1 TCP - ∆ - - nS WR Pulse Width TDWR 6 TCP - ∆ 6 TCP - nS Note: " ∆" (due to buffer driving delay and wire loading) is 20 nS. Port Access Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low TPDS 1 TCP - - nS Port Input Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. |
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