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CY8C5867AXI-LP024 Datasheet(PDF) 85 Page - Cypress Semiconductor |
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CY8C5867AXI-LP024 Datasheet(HTML) 85 Page - Cypress Semiconductor |
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85 / 122 page  PRELIMINARY PSoC® 5LP: CY8C58LP Family Datasheet Document Number: 001-84932 Rev. ** Page 85 of 122 11.5.4 SAR ADC Figure 11-35. SAR ADC DNL vs Output Code, Bypassed Internal Reference Mode Figure 11-36. SAR ADC INL vs Output Code, Bypassed Internal Reference Mode Table 11-28. SAR ADC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – – 12 bits Number of channels – single-ended – – No of GPIO Number of channels – differential Differential pair is formed using a pair of neighboring GPIO. –– No of GPIO/2 Monotonicity[45] Yes – – Ge Gain error[46] External reference – – ±0.1 % VOS Input offset voltage – – ±2 mV IDD Current consumption[45] –– 1 mA Input voltage range – single-ended[45] VSSA –VDDA V Input voltage range – differential[45] VSSA –VDDA V PSRR Power supply rejection ratio[45] 70 – – dB CMRR Common mode rejection ratio 70 – – dB INL Integral non linearity[45] VDDA 1.71 to 5.5 V, 1 Msps, VREF 1 to 5.5 V –– +2/–1.5 LSB VDDA 2.0 to 3.6 V, 1 Msps, VREF 2 to VDDA –– ±1.2 LSB VDDA 1.71 to 5.5 V, 500 ksps, VREF 1 to 5.5 V –– ±1.3 LSB DNL Differential non linearity[45] VDDA 1.71 to 5.5 V, 1 Msps, VREF 1 to 5.5 V –– +2/–1 LSB VDDA 2.0 to 3.6 V, 1 Msps, VREF 2 to VDDA No missing codes – – 1.7/–0.99 LSB VDDA 1.71 to 5.5 V, 500 ksps, VREF 1 to 5.5 V No missing codes – – +2/–0.99 LSB RIN Input resistance[45] –180 – kΩ Notes 45. Based on device characterization (Not production tested). 46. For total analog system Idd < 5 mA, depending on package used. With higher total analog system currents it is recommended that the SAR ADC be used in differential mode. |
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