ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet

ASCell3912

Rev. A, February 2000

Page 12 of 14

Austria Mikro Systeme International AG

Pin

Name

Type

Description

17

D_EN

O

Enable data bus

18

D_CLK

I

Clock for serial interface

19

DATA

I/O

Data Input / Output for serial interface

20

DVDD

P

Digital positive supply

4

Application Schematic

DC to 100 kHz

RF_LO = f

R F

G. Schultes, ISM868_RX

Revision: 0, 99 07 16

f/64

+/-45°

Protocol

Decoder

Receiver

Timing

0°

90°

Baseband

Amplifiers

Compe-

rators

Switchable

AC-Coupling

Baseband

Filters

Demodulator,

Synchronizer

Sync

Data

Loop-filter

Divider

XTAL+

XTAL-

Phase Detector

XTAL

Oscillator

Local

Oscillator

Quadrature

Down Converter

RE_INT

DATA

D_EN

D_CLK

WAKEUP

µC_CLK

DVCC

DGND

TEST

f =868.300 MHz

R F

Pre Filter

IRF

QDC

2*BBF

2*BBA

2*CMP

XTO

VCO

LPF

DIV PHD

2*ACC

DEM

AFC

LNA

DC-0

Bandwidth

Clock

AGND

AGND

AVDD

AVDD

LC-

GMC

Preamp.

PRA

RFGND

RF+

LC+

RF-

DVCC

DGND

Implementation

Example

Optional

Figure 6: Basic application schematic of the ASCell3912.