AD261

–5–

REV. 0

AD261-4

S0

F3

SYSTEM

FIELD

+5V dc

5V dc RTN

+5V dc

5V dc RTN

S1

S2

S3

S4

F0

F1

F2

F4

15

16

17

6

7

8

5

THREE-

STATE

LATCH

E

D

LINE 0

LATCH

E

D

THREE-

STATE

LINE 4

LINE 3

LATCH

E

D

THREE-

STATE

4

LATCH

E

D

THREE-

STATE

LINE 2

3

LATCH

E

D

THREE-

STATE

LINE 1

2

AD261-5

S0

F3

SYSTEM

FIELD

+5V dc

5V dc RTN

+5V dc

5V dc RTN

S1

S2

S3

S4

F0

F1

F2

F4

15

16

17

6

7

8

5

LATCH

E

D

THREE-

STATE

LINE 4

LINE 3

LATCH

E

D

THREE-

STATE

4

LATCH

E

D

THREE-

STATE

LINE 2

3

LATCH

E

D

THREE-

STATE

LATCH

E

D

THREE-

STATE

2

LINE 0

LINE 1

AD261 CONFIGURATIONS

(Continued from page 1)

Field and System Enable Functions: Both the isolated and

nonisolated sides of the AD261 have ENABLE pins that three-

state all outputs. Upon reenabling these pins, all outputs are

updated to reflect the current input logic level.

CE Certifiable: Simply by adding the external bypass capacitors

at the supply pins, the AD261 can attain CE certification in

most applications (to the EMC directive) and conformance to

the low voltage (safety) directive is assured by the EN60950

certification.

GENERAL ATTRIBUTES

The AD261 provides five HCMOS compatible isolated logic

lines with

≥ 10 kV/µs common-mode transient immunity.

The case design and pin arrangement provides greater than

18 mm spacing between field and system side conductors, pro-

viding CSA/IS and IEC creepage spacing consistent with 750 V

mains isolation.

The five unidirectional logic lines have six possible combina-

tions of “ins” and “outs,” or transmitter/receiver pairs; hence

there are six AD261 part configurations (see Table I).

Each 20 MHz logic line has a Schmidt trigger input and a three-

state output (on the other side of the isolation barrier) and 14 ns of

propagation delay. A single enable pin on either side of the

barrier causes all outputs on that side to go three-state and all

inputs (driven pins) to ignore their inputs and retain their last

known state.

Note: All unused logic inputs (1–5) should be tied either high or low,

but not left floating.

Edge “fidelity,” or the difference in propagation time for rising

and falling edges, is typically less than

±1 ns.

Power consumption, unlike opto-isolators, is a function of operat-

ing frequency. Each logic line barrier driver requires about 160

µA

per MHz and each receiver 40

µA per MHz plus, of course, 4 mA

total idle current (each side). The supply current diminishes

slightly with increasing temperature (about –0.03%/

°C).

The total capacitance spanning the isolation barrier is less than

10 pF.

The minimum period of a pulse that can be accurately coupled

across the barrier is about 25 ns. Therefore the maximum

square-wave frequency of operation is 20 MHz.

Table I. Model Number and Pinout Function

Pin

AD261-0

AD261-1 AD261-2 AD261-3 AD261-4 AD261-5

1

S0 (Xmt)

S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Rcv)

2

S1 (Xmt)

S1 (Xmt) S1 (Xmt) S1 (Xmt) S1 (Rcv)

S1 (Rcv)

3

S2 (Xmt)

S2 (Xmt) S2 (Xmt) S2 (Rcv)

S2 (Rcv)

S2 (Rcv)

4

S3 (Xmt)

S3 (Xmt) S3 (Rcv) S3 (Rcv)

S3 (Rcv)

S3 (Rcv)

5

S4 (Xmt)

S4 (Rcv)

S4 (Rcv) S4 (Rcv)

S4 (Rcv)

S4 (Rcv)

6

*

*

***

7

*

*

***

8

*

*

***

9–14

Not Present

15

**

*

*

16

*

*

***

17

*

***

18

F0 (Rcv)

F0 (Rcv)

F0 (Rcv) F0 (Rcv)

F0 (Rcv)

F0 (Xmt)

19

F1 (Rcv)

F1 (Rcv)

F1 (Rcv) F1 (Rcv)

F1 (Xmt) F1 (Xmt)

20

F2 (Rcv)

F2 (Rcv)

F2 (Rcv) F2 (Xmt) F2 (Xmt) F2 (Xmt)

21

F3 (Rcv)

F3 (Rcv)

F3 (Xmt) F3 (Xmt) F3 (Xmt) F3 (Xmt)

22

F4 (Rcv)

F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt)

*Pin function is the same on all models, as shown in the AD261-0 column.