ACT8828 datasheet(13/50 Pages) ACTIVE-SEMI

13 / 50 page

SYSTEM MANAGEMENT

ACT8828

Rev 7, 15-Nov-12

Innovative Power

- 13 -

www.active-semi.com

ActivePMU

TM and ActivePathTM are trademarks of Active-Semi.

2CTM is a trademark of NXP.

FUNCTIONAL DESCRIPTION

General Description

The ACT8828 offers a wide array of system

management functions that allow it to be configured

for optimal performance in a wide range of

applications.

2C Serial Interface

At the core of the ACT8828’s flexible architecture is

an I2C interface that permits optional programming

capability to enhance overall system performance.

To ensure compatibility with a wide range of system

processors, the ACT8828 uses standard I2C

commands; I2C write-byte commands are used to

program

the

ACT8828,

and

I2C

read-byte

commands are used to read the ACT8828’s internal

registers. The ACT8828 always operates as a slave

device, and is addressed using a 7-bit slave

address followed by an eighth bit, which indicates

whether the transaction is a read-operation or a

write-operation, [1011010x].

SDA is a bi-directional data line and SCL is a clock

input. The master initiates a transaction by issuing a

START condition, defined by SDA transitioning from

high to low while SCL is high. Data is transferred in

8-bit packets, beginning with the MSB, and is

clocked-in on the rising edge of SCL. Each packet

of data is followed by an “Acknowledge” (ACK) bit,

used to confirm that the data was transmitted

successfully.

For more information regarding the I2C 2-wire serial

interface, go to the NXP website: http://www.nxp.com

nPBIN Input

ACT8828's nPBIN pin is a dual-function pin,

combining system enable/disable control with a

hardware reset function. Refering to Figure 2, the

two pin functions are obtained by asserting this pin

low, either through a direct connection or through a

100kΩ resistor, as described below.

Figure 2:

nPBIN Input

In most applications, nPBIN will be driven through a

100kΩ resistor. When driven in this way, nPBIN

initiates system startup or shutdown, as described

in the System Startup and Shutdown section.

When a hardware-reset function is desired, nPBIN

may also be driven directly to GA. In this case,

nRSTO is immediately asserted low and remains

low until nPBIN is de-asserted and the reset timeout

period expires. This provides a hardware-reset

function, allowing the system to be manually reset if

the system processor locks up.

Although a typical application will use momentary

switches to drive nPBIN, as shown in Figure 2,

nPBIN may also be driven by other sources, such

as a GPIO or other logic output.

Enable/Disable Inputs (ON1, ON2, ON3,

and ON4)

The

ACT8828

provides

three

manual

enable/disable inputs, ON1, ON2, ON3, and ON4,

which enable and disable REG1, REG2, REG3, and

REG4 respectively. Once the system is enabled,

the system will remain enabled until all of ON1,

ON2, ON3, and ON4 have been de-asserted. See

the System Startup and Shutdown section for more

information.

Power-On Reset Output

nRSTO is an open-drain output which asserts low

upon startup or when nPBIN is driven directly to

GA, and remains asserted low until the 260msec

(default) power-on reset timer has expired. Connect

a 10kΩ or greater pull-up resistor from nRSTO to an

appropriate voltage supply.

nIRQ Output

nIRQ is an open-drain output that asserts low any

time nPBIN is asserted or an unmasked fault

condition exists. When asserted by nPBIN, nIRQ

automatically de-asserts when nPBIN is released.

When asserted by an unmasked fault condition,

nIRQ remains asserted until the microprocessor

polls the ACT8828's I2C interface. The ACT8828

supports a variety of other fault conditions, which

may each be optionally unmasked via the I2C

interface. For more information about the available

fault conditions, refer to the appropriate sections of

this datasheet.

Connect a pull-up resistor from nIRQ to an

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