AD524

REV. E

–8–

Theory of Operation

The AD524 is a monolithic instrumentation amplifier based on

the classic 3 op amp circuit. The advantage of monolithic con-

struction is the closely matched components that enhance the

performance of the input preamp. The preamp section develops

the programmed gain by the use of feedback concepts. The

values increase the gain) while the feedback forces the collector

currents Q1, Q2, Q3 and Q4 to be constant, which impresses

INPUT

20V p-p

100k

0.1%

10k

0.01%

1k

10T

10k

0.1%

AD524

1k

0.1%

100

0.1%

11k

0.1%

G = 10

G = 100

G = 1000

Figure 27. Settling Time Test Circuit

–IN

50 A

50 A

C4

C3

R53

20k

R54

20k

R52

20k

R55

20k

+IN

REFERENCE

SENSE

A3

50 A

50 A

R57

20k

R56

20k

A1

A2

4.44k

404

40

G100

G1000

Q2, Q4

Q1, Q3

Figure 28 Simplified Circuit of Amplifier; Gain Is Defined as

conductance of the input preamp increases to the transconduct-

ance of the input transistors. This has three important advantages.

First, this approach allows the circuit to achieve a very high

open loop gain of 3

reducing gain-related errors to a negligible 30 ppm. Second, the

gain bandwidth product, which is determined by C3 or C4 and

the input transconductance, reaches 25 MHz. Third, the input

voltage noise reduces to a value determined by the collector

current of the input transistors for an RTI noise of 7 nV/

√Hz at

G = 1000.

INPUT PROTECTION

As interface amplifiers for data acquisition systems, instrumen-

tation amplifiers are often subjected to input overloads, i.e.,

voltage levels in excess of the full scale for the selected gain

range. At low gains, 10 or less, the gain resistor acts as a current

limiting element in series with the inputs. At high gains the

excessive currents. Standard practice would be to place series

limiting resistors in each input, but to limit input current to

below 5 mA with a full differential overload (36 V) would re-

quire over 7k of resistance which would add 10 nV

√Hz of noise.

To provide both input protection and low noise a special series

protect FET was used.

A unique FET design was used to provide a bidirectional cur-

rent limit, thereby, protecting against both positive and negative

≈1 kΩ) in series with the input as

before. During an overload in the positive direction, a fourth

≈3 kΩ) in series with

the gate, which draws only the leakage current, and the FET

and when this FET goes into saturation, the gate current is

limited and the main FET will go into controlled enhancement.

The bidirectional limiting holds the maximum input current to

3 mA over the 36 V range.

INPUT OFFSET AND OUTPUT OFFSET

Voltage offset specifications are often considered a figure of

merit for instrumentation amplifiers. While initial offset may be

adjusted to zero, shifts in offset voltage due to temperature

variations will cause errors. Intelligent systems can often correct

for this factor with an autozero cycle, but there are many small-

signal high-gain applications that don’t have this capability.

AD712

1/2

9.09k

1k

100

16.2k

1/2

16.2k

1 F

1.62M

1.82k

10

100

1000

1 F

1 F

G1, 10, 100

G1000

AD524

DUT

Figure 29. Noise Test Circuit