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AD6426XST Datasheet(PDF) 12 Page - Analog Devices |
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AD6426XST Datasheet(HTML) 12 Page - Analog Devices |
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12 / 50 page ![]() Preliminary Technical Information AD6426 This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) - 12 - Confidential Information Table 4. H8 Peripheral Register Contents # 7 6 5 4 3 2 1 0 0 ODD 1 BRR[3:0] 2 TIE RIE TE RE AE DATEN CLKPOL CLKEN 3 Transmit[7:0] 4 TDRE RDRF ORER ERS PER TEND 5 Receive[7:0] 6 10 RxData[7:0] 10 TxData[7:0] 10 BRR[7:0] 11 EDSSI ELSI ETBEI ERBFI 11 BRR[15:8] 12 FIFO ST FIFO ST InterruptID[2:0] Int Pend 12 RxLevel[1:0] DMA TX FIFO RX FIFO FIFO EN 13 DLAB SET BRK Stick Par. Ev. Parity Parity EN Stop Bits WLS[1:0] 14 Loop Out2 Out1 RTS DTR 15 Error Rx FIFO TEMT THRE Break Interrupt Framing Error Parity Error Overrun Error Data Ready 16 DCD RI DSR CTS DDCD TERI DDSR DCTS 17 SCR[7:0] 18 RxData[7:0] 18 TxData[7:0] 19 MRESET UIB Enable PROC 26 TE RE FE PE BI OE 27 MODEM TX Level RX Time RX Level 28 Tx Trigger Level [3:0] Rx Trigger Level [3:0] 29 Chars in TX Buffer [3:0] Chars in Rx Buffer [3:0] 32 RxData[7:0] 32 TxData[7:0] 32 BRR[7:0] 33 EDSSI ELSI ETBEI ERBFI 33 BRR[15:8] 34 FIFO ST FIFO ST InterruptID[2:0] Int Pend R 35 DLAB SET BRK Stick Par. Ev. Parity Parity EN Stop Bits WLS[1:0] R/W 36 Loop Out2 Out1 RTS DTR 37 Error Rx FIFO TEMT THRE Break Interrupt Framing Error Parity Error Overrun Error Data Ready 38 DCD RI DSR CTS DDCD TERI DDSR DCTS 39 SCR[7:0] 48 TEST RX MODE CLOCK TX ENABLE CROSSPOINT SWITCH UCONN SWITCH R/W 49 SDORIE SDIROE IE SDIRIE SDOR EMT SDIR OE SDIR FULL 50 Receive[15:8] 51 Receive[7:0] 52 Transmit[15:8] 53 Transmit[7:0] 64/65 Data[7:0] |
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