AD6432AST datasheet(13/20 Pages) AD

13 / 20 page

AD6432

–13–

REV. 0

baseband converters. The interface between the AD6432 and

the AD6421 baseband converter is shown in Figure 35. The

AD7015 baseband converter provides a VR of 1.23 V; an auxil-

iary DAC in the AD7015 can be used to generate the AGC

voltage. Since it uses the same reference voltage, the numerical

input to this DAC provides an accurate RSSI value in digital

form, no longer requiring the reference voltage to have high

absolute accuracy.

Tunable Filter and I/Q Demodulators

The demodulators (I and Q) receive their inputs internally from

the IF amplifier through a two-pole tunable-frequency bandpass

filter. This filter is centered on the IF frequency and its band-

width is approximately equal to forty per cent of the IF fre-

quency. The filter attenuates the amount of noise present at the

input of the demodulators.

Each demodulator comprises a full-wave synchronous detector

followed by a 3 MHz, two-pole low-pass filter, producing differ-

ential outputs at pins IRXP and IRXN, and QRXP and QRXN.

Using the I and Q demodulators for IFs above 50 MHz is pre-

cluded by the 10 MHz to 50 MHz range of the PLL used in the

Demodulator section.

The I and Q outputs are differential and can swing up to 2 V p-p

at the low supply voltage of 2.7 V. They are nominally centered

at 1.5 V independent of power supply. They can therefore

directly drive the receive ADCs in the AD7015 or AD6421

baseband converters, which require an amplitude of 1.23 V to

fully load them when driven by a differential signal. The conver-

sion gain of the I and Q demodulators is 17 dB.

A simple 1-pole RC filter at the I and Q outputs, with its corner

above the modulation bandwidth is sufficient to attenuate un-

desired outputs. The design of the RC filter is eased by the

4.7 k

Ω resistor integrated into each I and Q output pin.

Phase-Locked Loop

The demodulators are driven by quadrature signals that are

provided by a variable-frequency quadrature oscillator (VFQO),

phase-locked to the reference frequency. This frequency is equal

or double the frequency of the signal applied to Pin FREF.

When the quadrature signals are at the IF, inphase and quadra-

ture baseband outputs are generated at the I output (IRXP

and IRXN) and Q output (QRXP and QRXN), respectively.

The quadrature accuracy of the VFQO is typically within

±1° at

26 MHz. A simplified diagram of the FREF input is shown in

Figure 32.

VPOS

Ω

20k

Ω

FREF

50 A PTAT

Figure 32. Simplified Schematic of the FREF Interface

The VFQO is controlled by the voltage between VPOS and

FLTR. In normal operation, a series RC network, forming the

PLL loop filter, is connected from FLTR to VPOS. The use of an

integral sample-hold system ensures that the frequency-

control voltage on Pin FLTR remains held during power-

down, so reacquisition of the carrier occurs in less than

µs.

In practice, the probability of a phase mismatch at power-

up is high, so the worst-case linear settling period to full

lock needs to be considered in making filter choices. This

is typically < 80

µs for a locking error of ±3° at an IF of

26 MHz. Note that the VFQO always provides quadrature

between its own I and Q outputs, but the phasing between

it and the reference carrier will swing around the final value

during the PLL’s settling time.

I and Q Transmit Modulator

The transmit modulator uses two standard mixer cells

whose linear inputs are the differential voltages at the input

Pins ITXP/ITXN and QTXP/QTXN, respectively and whose

local oscillator inputs are derived from a divide-by-two cell,

driven from the input applied to pins LOHI/LOLO. The

outputs of the mixers are summed and converted to single-

sided form. The output stage also filters the higher harmon-

ics, minimizing the need for filtering before this signal is

presented to the up-converter in a typical transmitter

configuration.

The I and Q inputs are intended to be driven using a

fully-differential drive (for example from an AD7015 or

AD6421) and need to be biased to a common-mode dc

level of 1.2 V, with a typical differential amplitude of

±1.028 V (that is, ±514 mV at each input). Some small

variation in the drive conditions is allowable, but will result

in nonoptimal performance. The minimum instantaneous

input should not go below 0.6 V and the maximum voltage

should not exceed 1.8 V using a 2.7 V supply (in general,

VP – 0.9 V). The impedance at these inputs is several M

Ω

in parallel with approximately 1 pF; the bias currents flow

out of the pins and are ~100 nA. These conditions permit

the use of a high impedance low-pass filter if desired ahead

of the modulator inputs.

The dc modulator output is at a constant dc level of 1.5 V,

independent of temperature and supply voltage. It is de-

signed to drive a 150

Ω load and should either be matched

into a 50

Ω load, using a simple LC network, or padded to

150

Ω with a series 100 Ω resistor (Figure 33). The output

is short-circuit-proof. The output modulated signal at pin

MODO has a power of –16 dBm when driving a 50

Ω load

with a 100

Ω series resistor, as shown in Figure 33. This

power is specified at a carrier frequency of 272 MHz with a

maximum dc differential signal applied to the I or Q chan-

nel while the other channel has no differential signal ap-

plied. The transmit modulator is enabled only when the

TXPU input (Pin 39) is taken HI.

Ω

100

Ω

MODO

100pF

Figure 33. Output Impedance of Pin MODO Is

Designed to Drive a 50

Ω Load with a 100 Ω Series

Resistor

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