AD800/AD802

REV. B

–9–

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

DATAOUT

DATAOUT

CLKOUT

CLKOUT

ASUBST

FRAC

FRAC

SUBST

DATAIN

DATAIN

DATAOUT

DATAOUT

CLKOUT

CLKOUT

Z1

AD800/802

J1

J2

R1

R2

R5 100

R10

R6 100

5.0V

R9

R12

R11

R7 100

R8 100

R3

R4

J3

J4

C10

0.1

100

100

154

154

154

154

100

100

R22

80.6

R21

80.6

R19

130

R20

130

FRAC

FRAC

5.0V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Z2

10H116

R24

130

R23

130

J5

J6

R26

80.6

R25

80.6

DATAIN

DATAIN

5.0V

0.1

0.1

0.1

C7 0.1

C6 0.1

0.1

C16

5.0V

5.0V

R16 100

5.0V

C13 0.1

100

100

154

154

0.1

C20

C21 0.1

5.0V

5.0V

C8

C9

0.1

C5

C4

C3

R13

R14

R15 100

R17

R18

C17 0.1

C14 0.1

C15 0.1

0.1

0.1

C12

C11

C19

0.1

C2

10

µF

5.0V

BYPASS

NETWORK

OUT

IN

Figure 22. Evaluation Board Schematic, Positive Supply

Table I. Evaluation Board, Positive Supply: Components List

Reference

Designator

Description

Quantity

R1–8, R15–18

Resistor, 100

Ω, 1%

12

R9–14

Resistor, 154

Ω, 1%

6

R19, 20, 23, 24

Resistor, 130

Ω, 1%

4

R21, 22, 25, 26

Resistor, 80.6

Ω, 1%

4

Capacitor, Loop Damping (See Specifications Page)

1

C2

Capacitor, 10

µF, Tantalum

1

C3–C21

Capacitor, 0.1

µF, Ceramic Chip

17

Z1

AD800/AD802

1

Z2

10H116, ECL Line Receiver

1

IN

0.1

µF

C2

10

µF

BYPASS

NETWORK

(A, B, C,

OR D)

TO DEVICE

IN

5.0V

BEADS WITH ONE LOOP

IN

0.1

µF

TO

DEVICE

TO

DEVICE

(A)

IN

0.1

µF

TO

DEVICE

BEAD WITH

ONE LOOP

(B)

(C)

BEAD WITH

TWO LOOPS

IN

0.1

µF

TO

DEVICE

BEAD WITH

TWO LOOPS

(D)

BEAD WITH

TWO LOOPS

BYPASS NETWORK

COMPONENTS:

CAPACITOR ..........CERAMIC CHIP

FERRITE BEAD......1/4 IN. STACKPOLE CARBO 57-1392

3.0

0

1.0

1.5

0.5

0.1

1.0

0

2.5

2.0

0.9

0.7

0.6

0.5

0.8

0.4

0.3

0.2

NOISE – V p-p @ 311MHz

(A)

(B)

(C)

(D)

Figure 23. Bypass Network Schemes

Figure 24. AD802-155 Output Jitter vs. Supply Noise

(PECL Configuration)