MMA955xL

Sensors

22

Freescale Semiconductor, Inc.

4.15

Slave SPI Timing

The following table describes the timing requirements for the SPI system. The “#” column refers to the numbered time period in

Figure 13.

Figure 13. SPI slave timing

Table 15. Slave SPI timing

#

Function

Symbol

Min

Max

Unit

—

Operating frequency

Hz

1

SCLK period

4—

2

Enable lead time

0.5

—

3

Enable lag time

0.5

—

4

Clock (SCLK) high or low time

200

—

ns

5

Data setup time (inputs)

15

—

ns

6

Data-hold time (inputs)

25

—

ns

7

Access time

—25

ns

8

SDO-disable time

—25

ns

9

Data valid (after SCLK edge)

—25

ns

10

Data-hold time (outputs)

0—

ns

11

Rise time

Input

Output

—

—

25

25

ns

ns

12

Fall time

Input

Output

—

—

25

25

ns

ns

SCLK

(INPUT)

SDI

(INPUT)

SDO

(OUTPUT)

SS

(INPUT)

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT

SLAVE LSB OUT

BIT 6 . . . 1

NOTE:

SLAVE

SEE

NOTE

1. Not defined but normally MSB of character just received.

12

1

<

11

3

4

24

7

5

6

9

8

10

10