EM47EM3288SBA

May. 2012

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AC Operating Test Characteristics

Symbol

Speed Bin

-125 (DDR3-1600)

-150 (DDR3-1333)

Units

Notes

CL-nRCD-nRP

11-11-11

9-9-9

Parameter

Min.

Max.

Min.

Max.

ODT to power-down entry/ exit

latency

WL–1

-

WL–1

-

nCK

ODT turn on latency

WL–2

WL–2

WL–2

WL–2

nCK

ODT turn off latency

WL–2

WL–2

WL–2

WL–2

nCK

ODT latency for changing from

RTT_Nom to RTT_WR

WL–2

WL–2

WL–2

WL–2

nCK

ODT latency for changing from

RTT_WR to RTT_Nom (BC4)

-

-

nCK

ODT latency for changing from

RTT_WR to RTT_Nom (BL8)

-

-

nCK

Note 1: Actual value dependant upon measurement level definitions which are TBD.

Note 2: Commands requiring a locked DLL are: READ (and READA) and synchronous ODT commands.

Note 3: The max values are system dependent.

Note 4: WR as programmed in mode register.

Note 5: Value must be rounded-up to next higher integer value.

Note 6: There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

Note 7: ODT turn on time (min.) is when the device leaves high impedance and ODT resistance begins to turn

on. ODT turn on time (max.) is when the ODT resistance is fully on. Both are measured from ODTLon.

Note 8: ODT turn-off time (min.) is when the device starts to turn-off ODT resistance. ODT turn-off time (max.)

is when the bus is in high impedance. Both are measured from ODTLoff.

Note 9: tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next

integer.

Note 10: WR in clock cycles as programmed in MR0.

Note 11: The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and

tHZ(DQS)max on the right side.

Note 12: Output timing deratings are relative to the SDRAM input clock. When the device is operated with input

clock jitter, this parameter needs to be derated by TBD.

Note 13: Value is only valid for RON34.

Note 14: Single ended signal parameter. Refer to the section of tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Notes

for definition and measurement method.

Note 15: tREFI depends on operating case temperature (Tc).

Note 16: tIS(base) and tIH(base) values are for 1V/ns command/ addresss single-ended slew rate and 2V/ns

CK, /CK differential slew rate, Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins

except RESET, VREF(DC) = VREFCA(DC). See Address / Command Setup, Hold and Derating section.

Note 17: tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, /DQS

differential slew rate. Note for DQ and DM signals, VREF(DC)= VREFDQ(DC). For input only pins except

RESET, VREF(DC) = VREFCA(DC). See Data Setup, Hold and and Slew Rate Derating section.