ADM1021 datasheet(2/12 Pages) AD

2 / 12 page

–2–

REV. 0

ADM1021–SPECIFICATIONS (T

A = TMIN to TMAX, VDD = 3.0 V to 3.6 V, unless otherwise noted)

Parameter

Min

Typ

Max

Units

Test Conditions/Comments

POWER SUPPLY AND ADC

Temperature Resolution

°C

Guaranteed No Missed Codes

Temperature Error, Local Sensor

±1

°C

–3

°C

Temperature Error, Remote Sensor

–3

°CT

A = +60

°C to +100°C

–5

°C

Supply Voltage Range

3.6

Note 1

Undervoltage Lockout Threshold

2.5

2.7

2.95

VDD Input, Disables ADC,

Rising Edge

Undervoltage Lockout Hysteresis

Power-On Reset Threshold

0.9

1.7

2.2

VDD, Falling Edge

POR Threshold Hysteresis

Standby Supply Current

µAV

DD = 3.3 V, No SMBus Activity

µA

SCLK at 10 kHz

Average Operating Supply Current

µA

0.25 Conversions/Sec Rate

Auto-Convert Mode, Averaged Over 4 Seconds

160

200

µA

2 Conversions/Sec Rate

Conversion Time

115

170

From Stop Bit to Conversion

Complete (Both Channels)

Remote Sensor Source Current

D+ Forced to D– + 0.65 V

130

µA

High Level

3.5

5.5

µA

Low Level

D-Source Voltage

0.7

Address Pin Bias Current (ADD0, ADD1)

µA

Momentary at Power-On Reset

SMBUS INTERFACE

Logic Input High Voltage, VIH

2.2

VDD = 3 V to 5.5 V

STBY, SCLK, SDATA

Logic Input Low Voltage, VIL

0.8

VDD = 3 V to 5.5 V

STBY, SCLK, SDATA

SMBus Output Low Sink Current

SDATA Forced to 0.6 V

ALERT Output Low Sink Current

ALERT Forced to 0.4 V

Logic Input Current, IIH, IIL

–1

µA

SMBus Input Capacitance, SCLK, SDATA

SMBus Clock Frequency

100

kHz

SMBus Clock Low Time, tLOW

4.7

µst

LOW Between 10% Points

SMBus Clock High Time, tHIGH

µst

HIGH Between 90% Points

SMBus Start Condition Setup Time, tSU:STA

4.7

µs

SMBus Repeat Start Condition

250

Between 90% and 90% Points

Setup Time, tSU:STA

SMBus Start Condition Hold Time, tHD:STA

µs

Time from 10% of SDATA to

90% of SCLK

SMBus Stop Condition Setup Time, tSU:STO

µs

Time from 90% of SCLK to 10%

of SDATA

SMBus Data Valid to SCLK

250

Time from 10% or 90% of

Rising Edge Time, tSU:DAT

SDATA to 10% of SCLK

SMBus Data Hold Time, tHD:DAT

µs

SMBus Bus Free Time, tBUF

4.7

µs

Between Start/Stop Condition

SCLK Falling Edge to SDATA

µs

Master Clocking in Data

Valid Time, tVD,DAT

NOTES

1Operation at V

DD = +5 V guaranteed by design, not production tested.

2Guaranteed by design, not production tested.

Specifications subject to change without notice.

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