REV. B

–12–

ADP3806

Shutdown

A high impedance CMOS logic input is provided to turn off the

ADP3806. When the voltage on

SD is less than 0.8 V, the

ADP3806 is placed in low power shutdown. With the exception

of the system current sense amplifier, AMP2, all other circuitry

is turned off. The reference and regulators are pulled to ground

during shutdown and all switching is stopped. During this state,

the supply current is less than 5

mA. Also, the BAT, CS+, CS–,

and SW pins go to high impedance to minimize current drain

from the battery.

UVLO

Undervoltage lock-out, UVLO, is included in the ADP3806 to

ensure proper startup. As VCC rises above 1 V, the reference

and regulators will track VCC until they reach their final volt-

ages. However, the rest of the circuitry is held off by the UVLO

comparator. The UVLO comparator monitors both regulators

to ensure that they are above 5 V before turning on the main

charger circuitry. This occurs when VCC reaches 6 V. Monitor-

ing the regulator outputs makes sure that the charger circuitry

and driver stage have sufficient voltage to operate normally. The

UVLO comparator includes 300 mV of hysteresis to prevent

oscillations near the threshold.

Startup Sequence

During a startup from either

SD going high or VCC exceeding

the UVLO threshold, the ADP3806 initiates a soft-start sequence.

The soft-start timing is set by the compensation capacitor at the

COMP pin and an internal 40

mA source. Initially, both DRVH

and DRVL are held low until VCOMP reaches 1 V. This delay

time is set by

t

CV

A

DELAY

COMP

=

¥1

40

m

(4)

For a 0.22

delay, the duty cycle is very low and then ramps up to its final

the charge current is equal to zero at first, DRVLSD is active

and DRVL will not turn on. However, if the BST capacitor is

discharged, DRVL will be forced on for a minimum on time

of 200 ns each clock period until the BST capacitor is charged

to greater than 4 V. Typically the BST capacitor is charged in five

to ten clock cycles.

Loop Feed Forward

As the startup sequence discussion shows, the response time at

COMP is slowed by the large compensation capacitor. To speed

up the response, two comparators can quickly feed forward around

the normal control loop and pull the COMP node down to limit

any overshoot in either short-circuit or overvoltage conditions.

The overvoltage comparator has a trip point set to 20% higher

than the final battery voltage. The overcurrent comparator thresh-

old is set to 180 mV across the CS pins, which is 15% above the

maximum programmable threshold. When these comparators

are tripped, a normal soft-start sequence is initiated. The over-

voltage comparator is valuable when the battery is removed

during charging. In this case, the current in the inductor causes

the output voltage to spike up, and the comparator limits the

maximum voltage. Neither of these comparators affects the loop

under normal charging conditions.

APPLICATION INFORMATION

Design Procedure

Refer to Figure 1, the typical application circuit, for the follow-

ing description. The design follows that of a buck converter.

With Li-Ion cells it is important to have a regulator with accu-

rate output voltage control.

Battery Voltage Settings

The ADP3806 has three options for voltage selection:

1. 12.525 V/16.7 V as selectable fixed voltages

2. 12.6 V/16.8 V as selectable fixed voltages

3. Adjustable

When using the fixed versions, R11 should be a short or 0

W

wire jumper and R12 should be an open circuit. When using the

adjustable version, the following equation gives the ratio of the

two resistors:

R

R

V

BAT

11

12

2 5

1

= ÊËÁ

ˆ

¯˜

.

–

(5)

Often 0.1% resistors are required to maintain the overall accu-

racy budget in the design.

Inductor Selection

Usually the inductor is chosen based on the assumption that the

inductor ripple current is

±15% of the maximum output dc

current at maximum input voltage. As long as the inductor used

has a value close to this, the system should work fine. The final

choice affects the trade-offs between cost, size, and efficiency.

For example, the lower the inductance, the size is smaller but

ripple current is higher. This situation, if taken too far, will lead

to higher ac losses in the core and the windings. Conversely, a

higher inductance results in lower ripple current and smaller

output filter capacitors, but the transient response will be slower.

With these considerations, the required inductance can be

found from

L

VV

I

DT

IN, MAX

BAT

MIN

S

1

=¥

¥

–

D

(6)

current is found from

DII

BAT, MAX

=¥

03

.

(7)

the maximum peak-to-peak ripple is 30%, that is 0.3, and maxi-

ms, the value of L1 is calculated as 18.9 mH.

Choosing the closest standard value gives L1 = 22

mH.

Output Capacitor Selection

An output capacitor is needed in the charger circuit to absorb

the switching frequency ripple current and smooth the output

voltage. The rms value of the output ripple current is given by

I

V

fL

DD

rms

IN, MAX

=

()

112

1–

(8)

The maximum value occurs when the duty cycle is 0.5. Thus

I

V

fL

rms_MAX

IN, MAX

= 0 072

1

.

(9)