ADSP-2181 datasheet(13/64 Pages) AD

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ADSP-21xx

REV. B

–13–

If the ADSP-21xx is performing an external memory access

when the external device asserts the BR signal, it will not three-

state the memory interfaces or assert the BG signal until the

cycle after the access completes (up to eight cycles later depend-

ing on the number of wait states). The instruction does not need

to be completed when the bus is granted; the ADSP-21xx will

grant the bus in between two memory accesses if an instruction

requires more than one external memory access.

When the BR signal is released, the processor releases the BG

signal, re-enables the output drivers and continues program

execution from the point where it stopped.

The bus request feature operates at all times, including when

the processor is booting and when RESET is active. If this

feature is not used, the BR input should be tied high (to VDD).

Low Power IDLE Instruction

The IDLE instruction places the ADSP-21xx processor in low

power state in which it waits for an interrupt. When an interrupt

occurs, it is serviced and execution continues with instruction

following IDLE. Typically this next instruction will be a JUMP

back to the IDLE instruction. This implements a low-power

standby loop.

The IDLE n instruction is a special version of IDLE that slows

the processor’s internal clock signal to further reduce power

consumption. The reduced clock frequency, a programmable

fraction of the normal clock rate, is specified by a selectable

divisor, n, given in the IDLE instruction. The syntax of the

instruction is:

IDLE n;

where n = 16, 32, 64, or 128.

The instruction leaves the chip in an idle state, operating at the

slower rate. While it is in this state, the processor’s other

internal clock signals, such as SCLK, CLKOUT, and the timer

clock, are reduced by the same ratio. Upon receipt of an

enabled interrupt, the processor will stay in the IDLE state for

up to a maximum of n CLKIN cycles, where n is the divisor

specified in the instruction, before resuming normal operation.

When the IDLE n instruction is used, it slows the processor’s

internal clock and thus its response time to incoming interrupts–

the 1-cycle response time of the standard IDLE state is in-

creased by n, the clock divisor. When an enabled interrupt is

received, the ADSP-21xx will remain in the IDLE state for up

to a maximum of n CLKIN cycles (where n = 16, 32, 64, or

128) before resuming normal operation.

When the IDLE n instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster rate than can be serviced, due to the additional time the

processor takes to come out of the IDLE state (a maximum of n

CLKIN cycles).

ADSP-216x Prototyping

You can prototype your ADSP-216x system with either the

ADSP-2101 or ADSP-2103 RAM-based processors. When code

is fully developed and debugged, it can be submitted to Analog

Devices for conversion into a ADSP-216x ROM product.

The ADSP-2101 EZ-ICE emulator can be used for develop-

ment of ADSP-216x systems. For the 3.3 V ADSP-2162 and

ADSP-2164, a voltage converter interface board provides 3.3 V

emulation.

Additional overlay memory is used for emulation of ADSP-

2161/62 systems. It should be noted that due to the use of off-

chip overlay memory to emulate the ADSP-2161/62, a perfor-

mance loss may be experienced when both executing instruc-

tions and fetching program memory data from the off-chip

overlay memory in the same cycle. This can be overcome by

locating program memory data in on-chip memory.

Ordering Procedure for ADSP-216x ROM Processors

To place an order for a custom ROM-coded ADSP-2161,

ADSP-2162, ADSP-2163, or ADSP-2164 processor, you must:

1. Complete the following forms contained in the ADSP ROM

Ordering Package, available from your Analog Devices sales

representative:

ADSP-216x ROM Specification Form

ROM Release Agreement

ROM NRE Agreement & Minimum Quantity Order (MQO)

Acceptance Agreement for Pre-Production ROM Products

2. Return the forms to Analog Devices along with two copies of

the Memory Image File (.EXE file) of your ROM code. The

files must be supplied on two 3.5" or 5.25" floppy disks for

the IBM PC (DOS 2.01 or higher).

3. Place a purchase order with Analog Devices for non-recurring

engineering changes (NRE) associated with ROM product

development.

After this information is received, it is entered into Analog

Devices’ ROM Manager System which assigns a custom ROM

model number to the product. This model number will be

branded on all prototype and production units manufactured to

these specifications.

To minimize the risk of code being altered during this process,

Analog Devices verifies that the .EXE files on both floppy disks

are identical, and recalculates the checksums for the .EXE file

entered into the ROM Manager System. The checksum data, in

the form of a ROM Memory Map, a hard copy of the .EXE file,

and a ROM Data Verification form are returned to you for

inspection.

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