CA16B2CNN datasheet(21/30 Pages) AGERE

21 / 30 page

Agere Systems Inc.

Advance Data Sheet

CA16-Type 2.5 Gbits/s DWDM Transponder with

March 2001

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Timing Characteristics (continued)

Forward Clocking

In some applications, it is necessary to forward-clock

the data in a SONET/SDH system. In this application,

the reference clock from which the high-speed serial

clock is synthesized and the parallel data clock both

originate from the same source on the customer appli-

cation circuit. The timing control logic in the CA16 tran-

sponder transmitter automatically generates an internal

load signal that has a fixed relationship to the reference

clock. The logic takes into account the variation of the

reference clock to the internal load signal over temper-

ature and voltage. The connections required to imple-

ment this clocking method are shown in Figure 7. The

setup and hold times for PICLK to TxD[0:15] must be

met by the customer logic.

Possible problems: to meet the jitter generation specifi-

cations required by SONET/SDH, the jitter of the refer-

ence clock must be minimized. It could be difficult to

meet the SONET jitter generation specifications using

a reference clock generated from the customer logic.

Figure 7. Forward Clocking of the CA16Transponder

CUSTOMER LOGIC

CA16 TRANSPONDER

FIFO

PLL

DIVIDER

TXREFCLK

PHERR

PHINIT

PCLK

PICLK

LOCKDET

TIMING

GENERATOR

INTERNAL

TXD[0:15]

CLOCK

DATA

CENTERS

FIFO

PCLK

OSCILLATOR

155.52 MHz

± 20 ppm

TXREFCLK

CLOCK

BUFFER

1-1122(F).a

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