LU5X34F datasheet(13/26 Pages) AGERE

13 / 26 page

Lucent Technologies Inc.

Preliminary Data Sheet

LU5X34F

July 2000

Quad Gigabit Ethernet Transceiver

Input/Output Information (continued)

Table 3e. Pinout—Common I/O

* For related information, see Table 18, Test Modes.

Table 3f. Pinout—Power I/O

Name

I/O

Level

Description

OLREF

K16

Input/

Output

Analog

PECL Level Set Resistor Terminal 1.

OLRVS

K17

Input/

Output

Analog

PECL Level Set Resistor Terminal 2.

LPWR

Input

TTL/

CMOS

Device Low-Power Mode.

RESETN

Input

TTL/

CMOS

Device Reset (Active-Low).

TEST5*

Input/

Output

TTL/

CMOS

Global Test Control Input/Output.

TEST4*

Input

TTL/

CMOS

Local Test Control Input.

TEST3*

Input

TTL/

CMOS

Local Test Control Input.

TEST2*

Input

TTL/

CMOS

Local Test Control Input.

TEST1*

Input

TTL/

CMOS

Local Test Control Input.

BYPPLL

Input

TTL/

CMOS

Test Control, PLL Bypass Mode.

REFCLK,

REFCLKN

K1, K2

Input

PECL or

TTL/

CMOS

Reference Clock Input (100 MHz—125 MHz).

Used by the transmitter PLL to generate the

1.0 Gbits/s— 1.25 Gbits/s serial data; has a +100 ppm

tolerance requirement.

Name

Description

VDD

D5, D8, D10, B13, H4, K4, P8, P10

Device Digital Power.

VDDP

G17, H16

PLL Power.

VDDTX

D16, D17, F17, G16, L15, N16, N14, T17,

High-Speed Analog Transmitter Power.

VDDR

H14, K14

High-Speed Analog Receiver Power.

VSS

B2, C3, D4, D9, H8, H9, H10, J4, J8, J9, J10,

K8, K9, K10, P4, P9, P14, R3, R15, T2, T16

Device Digital Ground.

VSSPH15, H17

PLL Ground.

VSST

B16, C15, D14, J14

High-Speed Analog Transmitter Ground.

VSSRX

C16, C17, E16, F16, K15, L14, P17, R17

High-Speed Analog Receiver Ground.

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