Production Data

WM8783

w

PD, August 2010, Rev 4.0

9

AUDIO INTERFACE TIMING

LRCLK (input)

ADCDAT (output)

Note – BCLK is generated internally to the WM8783, and is synchronised to LRCLK

BCLK (see note)

Figure 3 Audio Interface Timing

Test Conditions

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Interface Timing

ADCDAT propagation delay from BCLK falling edge

20

ns

Figure 4 Recommended LRCLK Transition Area for Optimum Performance

It is recommended that for optimum performance the LRCLK transition occurs during the MCLK low,

as shown in Figure 4 above.