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V2DIP2-48 Datasheet(PDF) 9 Page - Future Technology Devices International Ltd. |
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V2DIP2-48 Datasheet(HTML) 9 Page - Future Technology Devices International Ltd. |
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9 / 25 page ![]() ` Copyright © 2010 Future Technology Devices International Limited 8 Document Reference No.: FT_000237 V2DIP2-48 VNC2-48 Development Module Datasheet Version 1.01 Clearance No.: FTDI# 152 3.3 I/O Configuration Using The Jumper Pin Header Two three way jumper pin headers are provided to allow for simple configuration of the I/O on data and control bus pins of the 48 pin QFN Vinculum-II. This is done by a combination of pulling up or pulling down the 48 pin QFN Vinculum-II IOBUS25 (pin 46) and IOBUS26 (pin 47). The relevant portion of the V2DIP2-48 module schematic is shown in Figure 3.3 IOBUS25 IOBUS26 Figure 3.3 - V2DIP2 48 On-Board Jumper Pin Configuration. IOBUS25 (VNC2-48Q pin 47) IOBUS26 (VNC2-48Q pin 46) I/O Mode Pull-Up Pull-Up Serial UART Pull-Up Pull-Down SPI Pull-Down Pull-Up Parallel FIFO Pull-Down Pull-Down Serial UART Table 3.2 - V2DIP2 48 Port Selection Jumper Pins NOTE: This is only applicable when using VNC1L compatible firmware e.g. V2DAP2. Other wise the user can set the pins for their own use. |
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