MPC949

TIMING SOLUTIONS

BR1333 — Rev 6

3

MOTOROLA

ABSOLUTE MAXIMUM RATINGS*

Symbol

Parameter

Min

Max

Unit

VCC

Supply Voltage

–0.3

4.6

V

VI

Input Voltage

–0.3

VDD + 0.3

V

IIN

Input Current

TBD

TBD

mA

TStor

Storage Temperature Range

–40

125

°C

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those

indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.

DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

VIH

Input HIGH Voltage

(Except PECL_CLK)

2.0

3.60

V

VIL

Input LOW Voltage

(Except PECL_CLK)

0.8

V

VPP

Peak–to–Peak Input Voltage

PECL_CLK

300

1000

mV

VCMR

Common Mode Range

PECL_CLK

VCC – 2.0

VCC – 0.6

V

Note 1.

VOH

Output HIGH Voltage

2.5

V

IOH = –20mA (Note 2.)

VOL

Output LOW Voltage

0.4

V

IOL = 20mA (Note 2.)

IIN

Input Current

±120

µA

Note 3.

CIN

Input Capacitance

4

pF

Cpd

Power Dissipation Capacitance

25

pF

Per Output

ICC

Maximum Quiescent Supply Current

70

85

mA

1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within

the VCMR range and the input swing lies within the VPP specification.

2. The MPC949 outputs can drive series or parallel terminated 50

Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications

Info section).

3. Inputs have pull–up/pull–down resistors which affect input current.

AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

Fmax

Maximum Input Frequency

150

MHz

Note 4.

tPLH

Propagation Delay

PECL_CLK to Q

TTL_CLK to Q

4.0

4.2

6.5

7.5

9.0

10.6

ns

Note 4.

tPHL

Propagation Delay

PECL_CLK to Q

TTL_CLK to Q

3.8

4.0

6.2

7.2

8.6

10.5

ns

Note 4.

tsk(o)

Output–to–Output Skew

300

350

ps

Note 4.

tsk(pr)

Part–to–Part Skew

PECL_CLK to Q

TTL_CLK to Q

1.5

2.0

2.75

4.0

ns

Note 5.

tPZL,tPZH

Output Enable Time

3

11

ns

Note 4.

tPLZ,tPHZ

Output Disable Time

3

11

ns

Note 4.

tr, tf

Output Rise/Fall Time

0.10

1.0

ns

0.8V to 2.0V

4. Driving 50

Ω transmission lines terminated to VCC/2.

5. Part–to–part skew at a given temperature and voltage.