LSM330DLC datasheet(44/66 Pages) STMICROELECTRONICS

44 / 66 page

LSM330DLC

44/66

Doc ID 022162 Rev 2

8.4

CTRL_REG4_A (23h)

8.5

CTRL_REG5_A (24h)

I1_DRDY1

DRDY1 interrupt on INT1_A. Default value 0.

(0: Disable; 1: Enable)

I1_DRDY2

DRDY2 interrupt on INT1_A. Default value 0.

(0: Disable; 1: Enable)

I1_WTM

FIFO watermark interrupt on INT1_A. Default value 0.

(0: Disable; 1: Enable)

I1_OVERRUN

FIFO Overrun interrupt on INT1_A. Default value 0.

(0: Disable; 1: Enable)

Table 26.

CTRL_REG3_A description (continued)

Table 27.

CTRL_REG4_A register

0(1)

This bit must be set to ‘0’ for correct operation.

BLE

FS1

FS0

0(1)

SIM

Table 28.

CTRL_REG4_A description

BLE

Big/little endian data selection. Default value 0.

(0: Data LSb @ lower address; 1: Data MSb @ lower address)

FS1-FS0

Full Scale selection. default value: 00

(00: +/- 2G; 01: +/- 4G; 10: +/- 8G; 11: +/- 16G)

High resolution output mode: Default value: 0

(0: High resolution disable; 1: High resolution enable)

SIM

SPI serial interface mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

Table 29.

CTRL_REG5_A register

BOOT

FIFO_EN

LIR_INT1

D4D_INT1

0(1)

This bit must be set to ‘0’ for correct operation.

0(1)

Table 30.

CTRL_REG5_A description

BOOT

Reboot memory content. Default value: 0

(0: Normal mode; 1: reboot memory content)

FIFO_EN

FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO Enable)

LSM330DLC Datasheet(PDF) 44 Page - STMicroelectronics

LSM330DLC Datasheet(HTML) 44 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL