PAM8803 datasheet(9/13 Pages) PAM

9 / 13 page

Maximum Gain

Digital Volume Control (DVC)

Mute Operation

As shown in block diagram(page 2),the PAM8803

has two internal amplifiers stage. The first

stage's gain is externally con figurable, while the

second stage's is internally fixed in a fixed-gain,

inverting configuration. The closed-loop gain of

the first stage is set by selecting the ratio of R to

R while the second stage's gain is fixed at 2x.

Consequently, the differential gain for the IC is

A =20*log [2*(R /R )]

The PAM8803 sets maximum R =218k

minimum R =27k , thus the maximum closed-

gain is 24dB.

The PAM8803 features a digital volume control

which consists of the UP, DN and RST pins. An

internal clock is used where the clock frequency

value is determined from the following formula:

f= f

/ 2

The oscillator frequency f

value is 200kHz

typical,with ±20% tolerance.The DVC’s clock

frequency is 33Hz (cycle time

) typical.

Volume changes are then effected by toggling

either the UP or DN pins with a logic low. After a

period of 3.5 clocks pulses with either the UP or

DN pins held low, the volume will change to the

next specified step, either UP or DN, and

followed by a short delay. This delay decreases

the longer the line is held low, eventually

reaching a delay of zero. The delay allows the

user to pull the UP or DN terminal low once for

one volume change, or hold down to ramp

several volume changes. The delay is optimally

configured for push button volume control.

If either the UP or DN pin remains low after the

first volume transition the volume will change

again, but this time after 9.5 clock pulses. The

followed transition occurs at 2 clock pulses for

each volume transition. This is intended to

provide the user with a volume control that

pauses briefly after initial application, and then

slowly increases the rate of volume change as it

is continuously applied. This cycle is shown in

the timing diagram shown in figure 1.

There are 64 discrete gain settings ranging from

+24dB maximum to -75dB minimum. Upon device

power on or applied a logic low to the RST pin,

the amplifier's gain is set to a default value of

2.6dB. However, when coming out of mute mode,

the PAM8803 will revert back to its previous gain

setting. Volume levels for each step vary and are

specified in Gain Setting table on page 7.

If both the UP and DN pins are held high, no

volume change will occur. Trigger points for the

UP and DN pins are at 70% of V

minimum for a

logic high, and 20% of V

maximum for a logic

low. It is recommended, however, to toggle UP

a n dD Nb e t w e e nV

a n d G N Df o r b e s t

performance.

Figure 1.Timming Diagram

The

pin is an input for controlling the

output state of the PAM8803. A logic low on this

pin disables the outputs, and a logic high on this

pin enables the outputs. This pin may be used as

a quick disable or enable of the outputs without a

volume fade. Quiescent current is listed in the

electrical characteristic table. The

pin can

be left floating due to the pull-up internal.

CLK

OSC

MUTE

and

30ms

In order to reduce power consumption while not

in use, the PAM8803 contains shutdown circuitry

that is used to turn off the amplifier's bias

circuitry. This shutdown feature turns the

amplifier off when logic low is placed on the

pin. By switching the

pin connected

to GND, the PAM8803 supply current draw will be

minimized in idle mode. The

pin cannot be

left floating due to the pull-down internal.

Shutdown operation

SHDN

Application Information

Power Analog Microelectronics Inc

www.poweranalog.com

PAM8803

3W Filterless Stereo Class-D Audio Amplifier

with Digital Volume Control

3.5 cycles

9.5 cycles

2 cycles

UP/DN

VOLUME

LEVEL

12/2009 Rev 1.4

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