PIC16CE623 datasheet(26/114 Pages) MICROCHIP

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PIC16CE62X

DS40182D-page 26

 1998-2013 Microchip Technology Inc.

5.2

PORTB and TRISB Registers

PORTB is an 8-bit wide, bi-directional port. The

corresponding data direction register is TRISB. A '1' in

the TRISB register puts the corresponding output driver

in a high impedance mode. A '0' in the TRISB register

puts the contents of the output latch on the selected

pin(s).

Reading PORTB register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are first read, then

this value is modified and written to the port data latch.

Each of the PORTB pins has a weak internal pull-up

(

200 A typical). A single control bit can turn on all the

pull-ups.

This

done

clearing

the

RBPU

(OPTION<7>) bit. The weak pull-up is automatically

turned off when the port pin is configured as an output.

The pull-ups are disabled on Power-on Reset.

Four of PORTB’s pins, RB<7:4>, have an interrupt on

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB<7:4> pin con-

figured as an output is excluded from the interrupt on

change comparison). The input pins of RB<7:4> are

compared with the old value latched on the last read of

PORTB. The “mismatch” outputs of RB<7:4> are

OR’ed together to generate the RBIF interrupt (flag

latched in INTCON<0>).

FIGURE 5-5:

BLOCK DIAGRAM OF

RB<7:4> PINS

Data Latch

From other

RBPU(1)

VDD

I/O pin

Data Bus

WR PORTB

WR TRISB(1)

Set RBIF

TRIS Latch

RD TRISB

RD PORTB

RB<7:4> pins

weak

pull-up

RD Port

Latch

TTL

Input

Buffer

Note 1: TRISB = 1 enables weak pull-up if RBPU = '0'

(OPTION<7>).

Buffer

RB<7:6> in serial programming mode

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

Any read or write of PORTB. This will end the

mismatch condition.

Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with

software configurable pull-ups on these four pins allow

easy interface to a key pad and make it possible for

wake-up on key-depression. (See AN552, “Implement-

ing Wake-Up on Key Strokes”.)

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 5-6:

BLOCK DIAGRAM OF

RB<3:0> PINS

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF inter-

rupt flag may not get set.

Data Latch

RBPU(1)

VDD

Data Bus

WR PORTB

WR TRISB(1)

RD TRISB

RD PORTB

weak

pull-up

RD Port

RB0/INT

TTL

Input

Buffer

Note 1: TRISB = 1 enables weak pull-up if RBPU = '0'

(OPTION<7>).

Buffer

I/O pin

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