DSPIC33FJ64GP306A datasheet(68/362 Pages) MICROCHIP

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dsPIC33FJXXXGPX06A/X08A/X10A

DS70593D-page 68

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ister or WREG (with the exception of the MUL instruc-

tion), which writes the result to a register or register

pair. The MOV instruction allows additional flexibility and

can access the entire data space.

4.3.2

MCU INSTRUCTIONS

The 3-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where:

Operand

is always a working register (i.e., the

addressing mode can only be register direct) which is

referred to as Wb.

Operand

can be a W register, fetched from data

memory, or a 5-bit literal. The result location can be

either a W register or a data memory location. The

following addressing modes are supported by MCU

instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-bit or 10-bit Literal

TABLE 4-35:

FUNDAMENTAL ADDRESSING MODES SUPPORTED

4.3.3

MOVE AND ACCUMULATOR

INSTRUCTIONS

Move instructions and the DSP accumulator class of

instructions provide a greater degree of addressing

flexibility than other instructions. In addition to the

Addressing

modes

supported

most

MCU

instructions, move and accumulator instructions also

support Register Indirect with Register Offset

Addressing mode, also referred to as Register Indexed

mode.

In summary, the following Addressing modes are

supported by move and accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

4.3.4

MAC

INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,

EDAC

, MAC, MPY, MPY.N, MOVSAC and MSC), also referred

to as MAC instructions, utilize a simplified set of

addressing modes to allow the user to effectively

manipulate the data pointers through register indirect

tables.

The 2-source operand prefetch registers must be

members of the set {W8, W9, W10, W11}. For data

reads, W8 and W9 are always directed to the X RAGU

and W10 and W11 will always be directed to the Y

AGU. The effective addresses generated (before and

Note:

Not all instructions support all the

addressing

modes

given

above.

Individual

instructions

may

support

different subsets of these addressing

modes.

Addressing Mode

Description

File Register Direct

The address of the file register is specified explicitly.

The contents of a register are accessed directly.

The contents of Wn forms the EA.

The contents of Wn forms the EA. Wn is post-modified (incremented or

decremented) by a constant value.

Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.

The sum of Wn and a literal forms the EA.

Note:

For the MOV instructions, the Addressing

mode specified in the instruction can differ

for the source and destination EA.

However, the 4-bit Wb (Register Offset)

field is shared between both source and

destination (but typically only used by

one).

Note:

Not all instructions support all the

Addressing

modes

given

above.

Individual

instructions

may

support

different subsets of these Addressing

modes.

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