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PC56F8006VWL Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

Part # PC56F8006VWL
Description  Digital Signal Controller
PDF  106 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PC56F8006VWL Datasheet(HTML) 21 Page - Freescale Semiconductor, Inc

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Signal/Connection Descriptions
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
21
GPIOB1
(SS)
(SDA)
(ANA12 and
CMP2_P3)
27
2
30
2
Input/
Output
Input/
Output
Input/Open-
drain
Output
Analog
input
Input,
internal
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
SS — SS is used in slave mode to indicate to the SPI module that
the current transfer is to be received.
SDA — The I2C serial data line.
ANA12 and CMP2_P3 — Analog input to channel 12 of ADCA and
Positive input 3 of analog comparator 2.
When used as an analog input, the signal goes to the ANA12 and
CMP2_P3.
After reset, the default state is GPIOB1.
GPIOB2
(MISO)
(TIN2)
(ANA2 and
ANB2)
(CMP0_
OUT)
17
13
25
Input/
Output
Input/
Output
Input/
Output
Analog
Input
Output
Input,
internal
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
MISO — Master in/slave out. In master mode, this pin serves as the
data input. In slave mode, this pin serves as the data output. The
MISO line of a slave device is placed in the high-impedance state if
the slave device is not selected.
TIN2 — Dual timer module channel 2 input.
ANA2 and ANB2 — Analog input to channel 2 of ADCA and ADCB.
CMP0_OUT— Analog comparator 0 output.
When used as an analog input, the signal goes to the ANA2 and
ANB2.
After reset, the default state is GPIOB2.
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
Signal
Name
28
SOIC
32
LQFP
32
PSDI
P
48
LQFP
Type
State
During
Reset
Signal Description



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