ADC0834CCWMSLASHNOPB datasheet(6/40 Pages) TI

6 / 40 page

ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N

SNAS531B – AUGUST 1999 – REVISED MARCH 2013

www.ti.com

AC Characteristics

The following specifications apply for VCC = 5V, tr = tf = 20 ns and 25°C unless otherwise specified.

Tested

Design

Limit

Parameter

Conditions

Typ(1)

Limit(2)

Limit(3)

Units

Min

kHz

fCLK, Clock Frequency

Max

400

kHz

tC, Conversion Time

Not including MUX Addressing Time

1/fCLK

Min

Clock Duty Cycle(4)

Max

tSET-UP, CS Falling Edge or Data Input Valid

250

to CLK Rising Edge

tHOLD, Data Input Valid after CLK Rising

Edge

CL=100 pF

tpd1, tpd0—CLK Falling Edge to Output Data

Data MSB First

650

1500

Valid(5)

Data LSB First

250

600

CL=10 pF, RL=10k (See TRI-STATE

125

250

t1H, t0H,—Rising Edge of CS to Data Output

Test Circuits and Waveforms)

and SARS Hi–Z

CL=100 pf, RL=2k

500

CIN, Capacitance of Logic Input

COUT, Capacitance of Logic Outputs

(1)

Typicals are at 25°C and represent most likely parametric norm.

(2)

Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).

(3)

Ensured but not 100% production tested. These limits are not used to calculate outgoing quality levels.

(4)

A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty

cycle outside of these limits, the minimum, time the clock is high or the minimum time the clock is low must be at least 1

μs. The

maximum time the clock can be high is 60

μs. The clock can be stopped when low so long as the analog input voltage remains stable.

(5)

Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see

ADC0838-N Functional Block Diagram) to allow for comparator response time.

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Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N

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