M68ICS08GR datasheet(249/408 Pages) FREESCALE

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Communications Interface (SCI)

249

SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines

whether the receiver begins counting logic 1s as idle character bits

after the start bit or after the stop bit.

NOTE:

With the WAKE bit clear, setting the RWU bit after the RxD pin has been

idle may cause the receiver to wake up immediately.

18.5.3.9 Receiver Interrupts

The following sources can generate CPU interrupt requests from the SCI

receiver:

•

SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that

the receive shift register has transferred a character to the SCDR.

SCRF can generate a receiver CPU interrupt request. Setting the

SCI receive interrupt enable bit, SCRIE, in SCC2 enables the

SCRF bit to generate receiver CPU interrupts.

•

Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11

consecutive logic 1s shifted in from the PE1/RxD pin. The idle line

interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate

CPU interrupt requests.

18.5.3.10 Error Interrupts

The following receiver error flags in SCS1 can generate CPU interrupt

requests:

•

Receiver overrun (OR) — The OR bit indicates that the receive

shift register shifted in a new character before the previous

character was read from the SCDR. The previous character

remains in the SCDR, and the new character is lost. The overrun

interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI

error CPU interrupt requests.

•

Noise flag (NF) — The NF bit is set when the SCI detects noise on

incoming data or break characters, including start, data, and stop

bits. The noise error interrupt enable bit, NEIE, in SCC3 enables

NF to generate SCI error CPU interrupt requests.

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