M68ICS08GR datasheet(272/408 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908GR8 — Rev 4.0

272

System Integration Module (SIM)

MOTOROLA

–

Vector address generation

•

CPU enable/disable timing

•

Modular architecture expandable to 128 interrupt sources

Table 19-1 shows the internal signal names used in this section.

Figure 19-1. SIM Block Diagram

STOP/WAIT

CLOCK

CONTROL

CLOCK GENERATORS

POR CONTROL

RESET PIN CONTROL

SIM RESET STATUS REGISTER

INTERRUPT CONTROL

AND PRIORITY DECODE

MODULE STOP

MODULE WAIT

CPU STOP (FROM CPU)

CPU WAIT (FROM CPU)

SIMOSCEN (TO CGM)

CGMOUT (FROM CGM)

INTERNAL CLOCKS

MASTER

RESET

CONTROL

RESET

PIN LOGIC

LVI (FROM LVI MODULE)

ILLEGAL OPCODE (FROM CPU)

ILLEGAL ADDRESS (FROM ADDRESS

MAP DECODERS)

COP (FROM COP MODULE)

INTERRUPT SOURCES

CPU INTERFACE

RESET

CONTROL

SIM

COUNTER

COP CLOCK

CGMXCLK (FROM CGM)

÷ 2

VDD

INTERNAL

PULLUP

DEVICE

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