M68ICS08GR datasheet(352/408 Pages) FREESCALE

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Timer Interface Module (TIM)

Technical Data

MC68HC908GR8 — Rev 4.0

352

Timer Interface Module (TIM)

MOTOROLA

22.10.2 TIM Counter Registers

The two read-only TIM counter registers contain the high and low bytes

of the value in the TIM counter. Reading the high byte (TCNTH) latches

the contents of the low byte (TCNTL) into a buffer. Subsequent reads of

TCNTH do not affect the latched TCNTL value until TCNTL is read.

Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)

also clears the TIM counter registers.

NOTE:

If you read TCNTH during a break interrupt, be sure to unlatch TCNTL

by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL

retains the value latched during the break.

Address: T1CNTH, $0021 and T2CNTH, $002C

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

00000000

= Unimplemented

Figure 22-5. TIM Counter Registers High (TCNTH)

Address: T1CNTL, $0022 and T2CNTL, $002D

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

00000000

= Unimplemented

Figure 22-6. TIM Counter Registers Low (TCNTL)

Freescale Semiconductor, Inc.

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