M68ICS08GR datasheet(365/408 Pages) FREESCALE

365 / 408 page

Electrical Specifications

5.0 V DC Electrical Characteristics

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Electrical Specifications

365

Pullup resistors (as input only)

Ports PTA3/KBD3–PTA0/KBD0, PTC1–PTC0,

PTD6/T2CH0–PTD0/SS

RPU

Ω

Capacitance

Ports (as input or output)

COut

CIn

—

Monitor mode entry voltage

VTST

VDD +2.5

—

Low-voltage inhibit, trip falling voltage – target

VTRIPF

3.85

4.25

4.50

Low-voltage inhibit, trip rising voltage – target

VTRIPR

3.95

4.35

4.60

Low-voltage inhibit reset/recover hysteresis – target

(VTRIPF + VHYS = VTRIPR)

VHYS

—

100

—

POR rearm voltage(8)

VPOR

—

100

POR reset voltage(9)

VPORRST

700

800

POR rise time ramp rate(10)

RPOR

0.035

——

V/ms

Notes:

1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

2. Typical values reflect average measurements at midpoint of voltage range, 25

°C only.

3. Run (operating) IDD measured using external square wave clock source (fosc = 32.8 MHz). All inputs 0.2 V from rail. No

dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly

affects run IDD. Measured with all modules enabled.

4. Wait IDD measured using external square wave clock source (fosc = 32.8 MHz). All inputs 0.2 V from rail. No dc loads. Less

than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait

IDD. Measured with PLL and LVI enabled.

5. Stop IDD is measured with OSC1 = VSS.

6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 KHz). All inputs 0.2 V

from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.

7. Pullups and pulldowns are disabled. Port B leakage is specified in ADC Characteristics.

8. Maximum is highest voltage that POR is guaranteed.

9. Maximum is highest voltage that POR is possible.

10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum

VDD is reached.

Table 23-4. 5.0V DC Electrical Characteristics

Characteristic(1)

Symbol

Min

Typ(2)

Max

Unit

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

M68ICS08GR Datasheet(PDF) 365 Page - Freescale Semiconductor, Inc

M68ICS08GR Datasheet(HTML) 365 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL