WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port

Document Number: 001-86227 Rev. **

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next WM72016-6 memory location.

While the CS signal remains at a logic one, the WM72016-6

automatically increments an internal address pointer after every data word cycle has completed. The state of

the AUTOINCR bit in the Control/Status register and the contents of the Working Stored Address have no

impact on DSPI data streaming. Likewise, AUTOINCR and the Working Stored Address register are not

affected by DSPI serial port data streaming. The data streaming cycle is terminated once CS has been cleared

to a logic zero. The DSPI streaming capability removes the requirement for multiple instruction words, greatly

improving bandwidth requirements.

d14

d12

d10

d8

d6

d4

d2

d0

OP4 OP2 OP0

a8

a6

a4

a2

a0

d15

d13

d11

d9

d7

d5

d3

d1

WR

OP3 OP1

a9

a7

a5

a3

a1

CS

D0

D1

CLK

Figure 22. DSPI Write Cycle Detail

Note: In the event of a simultaneous memory access, the RFID request will take priority over the

secondary DSPI serial interface.

MICROCONTROLLER INTERRUPTS

The WM72016-6 is capable of generating interrupts initiated by a interrogator (RFID Reader) to a

microcontroller on the serial port. Interrupt generation provides a mechanism to alert a host microcontroller

that a RFID interrogator is present and to take control of the memory with no possibility of interruption from

the RFID interface.

During an interrupt, all RFID commands are disregarded until an INTEND DSPI

command is received to terminate the interrupt and return control back to the RFID interface.

An interrupt is generated from the WM72016-6 to the host by writing two standard Gen2 write cycles to USER

memory addresses 0x004 and 0x005. The XOR operation of the two data words written to the two respective

addresses must equal 0x1234. As with all Gen2 write commands, the WM72016-6 must be in the OPEN or

SECURED state prior to executing the write command sequence. Should the WM72016-6 RFID have a non-

zero ACCESS password, the device must be transitioned to the SECURED state by correctly accessing the tag

with the device‟s ACCESS password. The interrogator then transmits two cover-coded WRITE commands to

USER memory addresses 0x004 and 0x005 whose two data words when XORed together result in a value of

0x1234. A correct sequence of the WRITE commands will result in the WM72016-6 asserting an interrupt by

driving the DSPI CS high. Upon detection of a high state on the CS signal, the host microcontroller drives two

clock cycles (the two clock cycles are mandatory) on the DSPI CLK to acknowledge and clear the WM72016-

6 interrupt. The host microcontroller now has full and uninhibited access to the WM72016-6 memory. Any

attempted access by a RFID interrogator during this period will be disregarded until one of two conditions has

occurred:

The host microcontroller has released control of the WM72016-6 memory by writing an instruction

with the INTEND opcode, or

The WM72016-6 has been power-cycled.

The entire interrupt generation sequence is shown in Figure 23. Note that the values 0x1200 and 0x0034

shown in Figure 23 are shown for illustration purposes only – any two values whose XOR operation results in

a value of 0x1234 will generate a DSPI interrupt.

The host microcontroller releases its control of the

WM72016-6 memory by writing an instruction with an INTEND opcode refer to Table 9. The contents of the

DSPI write data word payload that follows the instruction word are ignored but must be present to constitute a

valid DSPI command.

Here are three important aspects to consider when using the interrupt mechanism: