PIC24FJ64GA002 datasheet(13/24 Pages) MICROCHIP

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DS80000470H-page 13

PIC24FJ64GA004 FAMILY

30. Module: UART (FIFO Error Flags)

Under certain circumstances, the PERR and

FERR error bits may not be correct for all bytes in

the receive FIFO. This has only been observed

when both of the following conditions are met:

• the UARTx receive interrupt is set to occur when

the FIFO is full or 3/4 full (UxSTA<7:6> = 1x),

and

• more than 2 bytes with an error are received.

In these cases, only the first two bytes, with a

parity or framing error, will have the corresponding

bits indicate correctly. The error bits will not be set

after this.

Work around

None.

Affected Silicon Revisions

31. Module: Core (BOR)

When the on-chip regulator is enabled (DISVREG

tied to VSS), a BOR event may spontaneously

occur under the following circumstances:

•VDD is less than 2.5V, and

• the internal band gap reference is being used as

a reference with the A/D Converter

(AD1PCFG<15> = 0)

Work around

Do not select the internal band gap as a reference

for the A/D Converter when the on-chip regulator

is in Tracking mode (LVDIF (IFS4<8>) = 1).

Affected Silicon Revisions

32. Module: Core (Instruction Set)

If an instruction producing a read-after-write stall

condition is executed inside a REPEAT loop, the

instruction will be executed fewer times than was

intended. For example, this loop:

repeat #0xf

inc [w1],[++w1]

will execute less than 16 times.

Work around

Avoid using REPEAT to repetitively execute

instructions that create a stall condition. Instead,

use a software loop using conditional branches.

The MPLAB® C Compiler will not generate

REPEAT

loops that cause this erratum.

Affected Silicon Revisions

33. Module: Memory (Program Space

Visibility)

When accessing data in the PSV area of data

RAM, it is possible to generate a false address

error trap condition by reading data located

precisely at the lower address boundary (8000h).

If data is read using an instruction with an auto-

decrement, the resulting RAM address will be

below the PSV boundary (i.e., at 7FFEh); this will

result in an address error trap.

This false address error can also occur if a 32-bit

MOV

instruction is used to read the data at location,

8000h.

Work around

Do not use the first location of a PSV page

(address 8000h).

The MPLAB C Compiler (v3.11 or later) supports

the option, -merrata=psv_trap, to prevent it

from generating code that would cause this

erratum.

Affected Silicon Revisions

A3/

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