CY7C344-15PCSLASHPI datasheet(5/15 Pages) CYPRESS

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CY7C344

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Document #: 38-03006 Rev. *B

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tPO

Asynchronous Preset to Registered Output

Delay[4]

Com’l /Ind

Mil

tCF

Synchronous Clock to Local Feedback Input[4,13] Com’l /Ind

Mil

External Synchronous Clock Period (1/fMAX3)[4]

Com’l/Ind

Mil

fMAX1

External Maximum Frequency(1/(tCO1 + tS))[4, 14] Com’l/Ind

50.0

41.6

33.3

MHz

Mil

50.0

41.6

33.3

fMAX2

Maximum Frequency with Internal Only

Feedback (1/(tCF + tS))[4, 15]

Com’l/Ind

71.4

62.5

45.4

MHz

Mil

71.4

62.5

45.4

fMAX3

Data Path Maximum Frequency, least of

1/(tWL + tWH), 1/(tS + tH), or (1/tCO1)[4, 16]

Com’l/Ind

83.3

71.4

62.5

MHz

Mil

83.3

71.4

62.5

fMAX4

Maximum Register Toggle Frequency

1/(tWL + tWH)[4, 17]

Com’l/Ind

83.3

71.4

62.5

MHz

Mil

83.3

71.4

62.5

tOH

Output Data Stable Time from Synchronous

Clock Input[4, 18]

Com’l/Ind

Mil

Notes:

13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, tS, is the minimum internal

period for an internal state machine configuration. This parameter is tested periodically by sampling production material.

14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate.

15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must

also control external points, this frequency can still be observed as long as it is less than 1/tCO1. This specification assumes no expander logic is used. This parameter

is tested periodically by sampling production material.

16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that no

expander logic is used.

17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a clock

signal applied to either a dedicated input pin or an I/O pin.

18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.

External Synchronous Switching Characteristics Over Operating Range (continued)[7]

Parameter

Description

7C344-15

7C344-20

7C344-25

Unit

Min.

Max.

Min.

Max.

Min.

Max.

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