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ICS810001-21 Datasheet(PDF) 2 Page - Integrated Device Technology |
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ICS810001-21 Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 19 page ![]() ICS810001DK-21 REVISION B APRIL 13, 2010 2 ©2010 Integrated Device Technology, Inc. ICS810001-21 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Block Diagram Pin Assignment Charge Pump VCXO V3:V0 Phase Detector Q Output Divider 00 = 4 (default) 01 = 8 10 = 12 11 = 18 VCXO Feedback Divider (M Value from Table) VCXO Input Pre-Divider (P Value from Table) VCXO Jitter Attenuation PLL Loop Filter VCXO Divider Table OE 01 MF MR Master Reset 0 1 CLK0 CLK1 CLK_SEL N1:N0 4 2 11 10 10 11 01 01 10 11 00 2 nBP1:nBP0 FemtoClock Frequency Multiplier 0= x22 (default) 1= x24 Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pullup Pullup 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 LF1 LF0 ISET VDD nBP0 GND CLK_SEL CLK1 N0 N1 nBP1 OE GND Q VDDO VDDA ICS810001-21 32 Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View |
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