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A40MX02-PL100M Datasheet(PDF) 73 Page - Microsemi Corporation |
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A40MX02-PL100M Datasheet(HTML) 73 Page - Microsemi Corporation |
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73 / 142 page ![]() 40MX and 42MX FPGA Families Re vi s i on 11 1 - 69 TTL Output Module Timing5 tDLH Data-to-Pad HIGH 2.4 2.7 3.1 3.6 5.1 ns tDHL Data-to-Pad LOW 2.8 3.2 3.6 4.2 5.9 ns tENZH Enable Pad Z to HIGH 2.5 2.8 3.2 3.8 5.3 ns tENZL Enable Pad Z to LOW 2.8 3.1 3.5 4.2 5.9 ns tENHZ Enable Pad HIGH to Z 5.2 5.7 6.5 7.6 10.7 ns tENLZ Enable Pad LOW to Z 4.8 5.3 6.0 7.1 9.9 ns tGLH G-to-Pad HIGH 2.9 3.2 3.6 4.3 6.0 ns tGHL G-to-Pad LOW 2.9 3.2 3.6 4.3 6.0 ns tLSU I/O Latch Output Set-Up 0.5 0.5 0.6 0.7 1.0 ns tLH I/O Latch Output Hold 0.0 0.0 0.0 0.0 0.0 ns tLCO I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O 5.6 6.1 6.9 8.1 11.4 ns tACO Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O 10.6 11.8 13.4 15.7 22.0 ns dTLH Capacitive Loading, LOW to HIGH 0.04 0.04 0.04 0.05 0.07 ns/pF dTHL Capacitive Loading, HIGH to LOW 0.03 0.03 0.03 0.04 0.06 ns/pF Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued) (Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) –3 Speed –2 Speed –1 Speed Std Speed –F Speed Parameter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. |
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