EVAL-ADF7012DBZ1 datasheet(12/28 Pages) AD

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ADF7012

Rev. A | Page 12 of 28

CIRCUIT DESCRIPTION

PLL OPERATION

A fractional-N PLL allows multiple output frequencies to be

generated from a single-reference oscillator (usually a crystal)

simply by changing the programmable N value found in the

N register. At the phase frequency detector (PFD), the reference

is compared to a divided-down version of the output frequency

(VCO/N). If VCO/N is too low a frequency, typically the output

frequency is lower than desired, and the PFD and charge-pump

combination sends additional current pulses to the loop filter.

This increases the voltage applied to the input of the VCO.

Because the VCO of the ADF7012 has a positive frequency vs.

voltage characteristic, any increase in the VTUNE voltage applied

to the VCO input increases the output frequency at a rate of

kilovolts, the tuning sensitivity of the VCO (MHz/V). At each

interval of 1/PFD seconds, a comparison is made at the PFD

until the PFD and charge pump eventually force a state of

equilibrium in the PLL where PFD frequency = VCO/N. At

this point, the PLL can be described as locked.

PFD

CRYSTAL/R

LOOP FILTER

FVCO

VCO

VCO/N

Figure 26. Fractional-N PLL

PFD

CRYSTAL

OUT

(1)

For a fractional-N PLL

⎟

⎠

⎞

⎜

⎝

⎛

FRAC

INT

PFD

OUT

(2)

where NFRAC can be Bits M1 to M12 in the fractional-N register.

CRYSTAL OSCILLATOR

The on-board crystal oscillator circuitry (Figure 27) allows an

inexpensive quartz crystal to be used as the PLL reference. The

oscillator circuit is enabled by setting XOEB low. It is enabled by

default on power-up and is disabled by bringing CE low. Errors

in the crystal can be corrected using the error correction

A single-ended reference may be used instead of a crystal, by

applying a square wave to the OSC2 pin, with XOEB set high.

OSC1

CP1

CP2

OSC2

Figure 27. Oscillator Circuit on the ADF7012

Two parallel resonant capacitors are required for oscillation at

the correct frequency—the value of these depend on the crystal

specification. They should be chosen so that the series value of

capacitance added to the PCB track capacitance adds to give the

load capacitance of the crystal, usually 20 pF. Track capacitance

values vary between 2 pF to 5 pF, depending on board layout.

Where possible, to ensure stable frequency operation over all

conditions, capacitors should be chosen so that they have a

very low temperature coefficient and/or opposite temperature

coefficients

Typically, for a 10 MHz crystal with 20 pF load capacitance,

the oscillator circuit can tolerate a crystal ESR value of ≤ 50 Ω.

The ESR tolerance of the ADF7012 decreases as crystal fre-

quency increases, but this can be offset by using a crystal with

lower load capacitance.

CRYSTAL COMPENSATION REGISTER

The ADF7012 features a 15-bit fixed modulus, which allows the

output frequency to be adjusted in steps of FPFD/15. This fine

resolution can be used to easily compensate for initial error and

temperature drift in the reference crystal.

FADJUST = FSTEP × FEC

(3)

where:

FSTEP = FPFD/215

FEC = Bit F1 to Bit F11 in the R Register

Note that the notation is twos complement, so F11 represents

the sign of the FEC number.

Example

FPFD = 10 MHz

FADJUST = −11 kHz

FSTEP = 10 MHz/215 = 305.176 Hz

FEC = −11 kHz/305.17 Hz = −36 = −(00000100100) =

11111011100 = 0x7DC

CLOCK OUT CIRCUIT

The clock out circuit takes the reference clock signal from the

Crystal Oscillator section and supplies a divided-down 50:50

mark-space signal to the CLKOUT pin. An even divide from

2 to 30 is available. This divide is set by the DB[19:22] in the

R register. On power-up, the CLKOUT defaults to divide by 16.

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