ADSP-BF522 datasheet(19/88 Pages) AD

19 / 88 page

Rev. D

Page 19 of 88

July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

version 2.1. An I2C multiplexer can be used to select one

processor at a time when booting multiple processors from

a single TWI.

• Boot from UART0 host on Port G (BMODE = 0x7) —

Using an autobaud handshake sequence, a boot-stream for-

matted program is downloaded by the host. The host

selects a bit rate within the UART clocking capabilities.

When performing the autobaud, the UART expects a “@”

(0x40) character (eight bits data, one start bit, one stop bit,

no parity bit) on the UART0RX pin to determine the bit

rate. The UART then replies with an acknowledgement

composed of 4 bytes (0xBF, the value of UART0_DLL, the

value of UART0_DLH, then 0x00). The host can then

download the boot stream. To hold off the host the Blackfin

processor signals the host with the boot host wait

(HWAIT) signal. Therefore, the host must monitor

HWAIT before every transmitted byte.

• Boot from UART1 host on Port F (BMODE = 0x8). Same

as BMODE = 0x7 except that the UART1 port is used.

• Boot from SDRAM (BMODE = 0xA) This is a warm boot

scenario, where the boot kernel starts booting from address

0x0000 0010. The SDRAM is expected to contain a valid

boot stream and the SDRAM controller must be configured

by the OTP settings.

• Boot from OTP memory (BMODE = 0xB) — This provides

a stand-alone booting method. The boot stream is loaded

from on-chip OTP memory. By default, the boot stream is

expected to start from OTP page 0x40 and can occupy all

public OTP memory up to page 0xDF. This is 2560 bytes.

Since the start page is programmable, the maximum size of

the boot stream can be extended to 3072 bytes.

• Boot from 8-bit external NAND flash memory (BMODE =

0xC and BMODE = 0xD) — In this mode, auto detection of

the NAND flash device is performed.

BMODE = 0xC, the processor configures PORTF GPIO

pins PF7:0 for the NAND data pins and PORTH pins

PH15:10 for the NAND control signals.

BMODE = 0xD, the processor configures PORTH GPIO

pins PH7:0 for the NAND data pins and PORTH pins

PH15:10 for the NAND control signals.

For correct device operation pull-up resistors are required

on both ND_CE (PH10) and ND_BUSY (PH13) signals. By

default, a value of 0x0033 is written to the NFC_CTL regis-

ter. The booting procedure always starts by booting from

byte 0 of block 0 of the NAND flash device.

NAND flash boot supports the following features:

—Device Auto Detection

—Error Detection & Correction for maximum reliability

—No boot stream size limitation

—Peripheral DMA providing efficient transfer of all data

(excluding the ECC parity data)

—Software-configurable boot mode for booting from

boot streams spanning multiple blocks, including bad

blocks

—Software-configurable boot mode for booting from

multiple copies of the boot stream, allowing for han-

dling of bad blocks and uncorrectable errors

—Configurable timing via OTP memory

Small page NAND flash devices must have a 512-byte page

size, 32 pages per block, a 16-byte spare area size, and a bus

configuration of 8 bits. By default, all read requests from

the NAND flash are followed by four address cycles. If the

NAND flash device requires only three address cycles, the

device must be capable of ignoring the additional address

cycles.

The small page NAND flash device must comply with the

following command set:

—Reset: 0xFF

—Read lower half of page: 0x00

—Read upper half of page: 0x01

—Read spare area: 0x50

For large-page NAND-flash devices, the four-byte elec-

tronic signature is read in order to configure the kernel for

booting, which allows support for multiple large-page

devices. The fourth byte of the electronic signature must

comply with the specification in Table 9 on Page 20.

Any NAND flash array configuration from Table 9, exclud-

ing 16-bit devices, that also complies with the command set

listed below are directly supported by the boot kernel.

There are no restrictions on the page size or block size as

imposed by the small-page boot kernel.

For devices consisting of a five-byte signature, only four are

read. The fourth must comply as outlined above.

Large page devices must support the following command

set:

—Reset: 0xFF

—Read Electronic Signature: 0x90

—Read: 0x00, 0x30 (confirm command)

Large-page devices must not support or react to NAND

flash command 0x50. This is a small-page NAND flash

command used for device auto detection.

By default, the boot kernel will always issue five address

cycles; therefore, if a large page device requires only four

cycles, the device must be capable of ignoring the addi-

tional address cycles.

• Boot from 16-Bit Host DMA (BMODE = 0xE) — In this

mode, the host DMA port is configured in 16-bit Acknowl-

edge mode, with little endian data formatting. Unlike other

modes, the host is responsible for interpreting the boot

stream. It writes data blocks individually into the Host

DMA port. Before configuring the DMA settings for each

block, the host may either poll the ALLOW_CONFIG bit in

HOST_STATUS or wait to be interrupted by the HWAIT

ADSP-BF522 Datasheet(PDF) 19 Page - Analog Devices

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