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PIC16F1825T-ESS Datasheet(PDF) 217 Page - Microchip Technology |
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PIC16F1825T-ESS Datasheet(HTML) 217 Page - Microchip Technology |
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217 / 448 page  2010-2012 Microchip Technology Inc. DS41440C-page 217 PIC16(L)F1825/1829 24.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. 24.2.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 “Alternate Pin Function” for more information. TABLE 24-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON1 — — SDO2SEL(2) SS2SEL(2) P1DSEL P1CSEL P2BSEL CCP2SEL 122 CCP1CON P1M<1:0>(1) DC1B<1:0> CCP1M<3:0> 236 CCP2CON P2M<1:0>(1) DC2B<1:0> CCP2M<3:0> 236 CCP3CON — — DC3B<1:0> CCP3M<3:0> 236 CCP4CON — — DC4B<1:0> CCP4M<3:0> 236 CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 214* CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 214* INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 127 INLVLC INLVLC7(2) INLVLC6(2) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 138 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 91 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 92 PIE3 — — CCP4IE CCP3IE TMR6IE —TMR4IE — 93 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 95 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF 96 PIR3 — — CCP4IF CCP3IF TMR6IF — TMR4IF — 97 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC —TMR1ON 195 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 196 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 191* TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 191* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 TRISC TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 136 Legend: — Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode. * Page provides register information. Note 1: Applies to ECCP modules only. 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. |
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