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PIC16F1825T-ESS Datasheet(PDF) 100 Page - Microchip Technology |
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PIC16F1825T-ESS Datasheet(HTML) 100 Page - Microchip Technology |
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100 / 448 page  PIC16(L)F1825/1829 DS41440C-page 100 2010-2012 Microchip Technology Inc. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 141 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 141 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 140 IOCBF(1) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 142 IOCBN(1) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 142 IOCBP(1) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 141 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 91 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 92 PIE4(1) — — — — — — BCL2IE SSP2IE 94 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 95 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF 96 PIR4(1) — — — — — — BCL2IF SSP2IF 98 STATUS — — —TO PD Z DC C 24 WDTCON — — WDTPS<4:0> SWDTEN 103 Legend: — Unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode. Note 1: PIC16(L)F1829 only. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) CLKOUT(2) Interrupt flag GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed PC PC + 1 PC + 2 Inst(PC) = Sleep Inst(PC - 1) Inst(PC + 1) Sleep Processor in Sleep Interrupt Latency(4) Inst(PC + 2) Inst(PC + 1) Inst(0004h) Inst(0005h) Inst(0004h) Dummy Cycle PC + 2 0004h 0005h Dummy Cycle TOST(3) PC + 2 Note 1: XT, HS or LP Oscillator mode assumed. 2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. 3: TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes. 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. |
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