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DSPIC33FJ32MC302EMM Datasheet(PDF) 14 Page - Microchip Technology |
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DSPIC33FJ32MC302EMM Datasheet(HTML) 14 Page - Microchip Technology |
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14 / 460 page  dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 DS70291G-page 14 © 2007-2012 Microchip Technology Inc. TMS TCK TDI TDO I I I O ST ST ST — No No No No JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. INDX1 QEA1 QEB1 UPDN1 I I I O ST ST ST CMOS Yes Yes Yes Yes Quadrature Encoder Index1 Pulse input. Quadrature Encoder Phase A input in QEI1 mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI1 mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Counter Direction State. INDX2 QEA2 QEB2 UPDN2 I I I O ST ST ST CMOS Yes Yes Yes Yes Quadrature Encoder Index2 Pulse input. Quadrature Encoder Phase A input in QEI2 mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI2 mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Counter Direction State. C1RX C1TX I O ST — Yes Yes ECAN1 bus receive pin. ECAN1 bus transmit pin. RTCC O — No Real-Time Clock Alarm Output. CVREF O ANA No Comparator Voltage Reference Output. C1IN- C1IN+ C1OUT I I O ANA ANA — No No Yes Comparator 1 Negative Input. Comparator 1 Positive Input. Comparator 1 Output. C2IN- C2IN+ C2OUT I I O ANA ANA — No No Yes Comparator 2 Negative Input. Comparator 2 Positive Input. Comparator 2 Output. PMA0 PMA1 PMA2 -PMPA10 PMBE PMCS1 PMD0-PMPD7 PMRD PMWR I/O I/O O O O I/O O O TTL/ST TTL/ST — — — TTL/ST — — No No No No No No No No Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes). Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select 1 Strobe. Parallel Master Port Data (Demultiplexed Master mode) or Address/ Data (Multiplexed Master modes). Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. DAC1RN DAC1RP DAC1RM O O O — — — No No No DAC1 Negative Output. DAC1 Positive Output. DAC1 Output indicating middle point value (typically 1.65V). DAC2RN DAC2RP DAC2RM O O O — — — No No No DAC2 Negative Output. DAC2 Positive Output. DAC2 Output indicating middle point value (typically 1.65V). TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Type Buffer Type PPS Description Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer |
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