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DSPIC33FJMC202ESS Datasheet(PDF) 287 Page - Microchip Technology |
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DSPIC33FJMC202ESS Datasheet(HTML) 287 Page - Microchip Technology |
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287 / 330 page  © 2007-2012 Microchip Technology Inc. DS70283K-page 287 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS TABLE 25-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No. Symbol Characteristic(1) Min Typ Max Units Conditions HSP35 TscH2doV, TscL2doV SDOx Data Output Valid after SCKx Edge —— 35 ns — HSP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 25 — — ns — HSP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 25 — — ns — HSP51 TssH2doZ SSx ↑ to SDOx Output High-Impedance 15 — 55 ns See Note 2 Note 1: These parameters are characterized but not tested in manufacturing. 2: Assumes 50 pF load on all SPIx pins. AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No. Symbol Characteristic(1) Min Typ Max Units Conditions HSP35 TscH2doV, TscL2doV SDOx Data Output Valid after SCKx Edge — — 35 ns — HSP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 25 — — ns — HSP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 25 — — ns — HSP51 TssH2doZ SSx ↑ to SDOX Output High-Impedance 15 — 55 ns See Note 2 HSP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 55 ns — Note 1: These parameters are characterized but not tested in manufacturing. 2: Assumes 50 pF load on all SPIx pins. TABLE 25-14: INTERNAL RC ACCURACY AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for Extended Param No. Characteristic Min Typ Max Units Conditions LPRC @ 32.768 kHz(1,2) HF21 LPRC -70 — +70 % -40°C ≤TA ≤+150°C VDD = 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes. 2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 21.4 “Watchdog Timer (WDT)” for more information. |
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