IR3827 datasheet(21/44 Pages) IRF

21 / 44 page

IR3827

www.irf.com

July 18, 2013

directly connected to the PVin pin to bypass the

internal LDO and therefore to avoid the voltage drop

on the internal LDO. This configuration is illustrated

in Figure 11.

Figure 12 shows the configuration using an external

VCC voltage. With this configuration, the input voltage

range can be extended down to 1.0V. Please note

that the input feedforward function is disabled for

this

configuration.

The

feedback

compensation

needs to be adjusted accordingly.

It should be noted as the VCC voltage decreases, the

efficiency and the over current limit will decrease

due to the increase of RDS(ON). Please refer to the

section of the over current protection for more

information.

Figure 10 LDO Dropout Voltage at Vin=PVin=5V

IR3827

VCC/

LDO_OUT

PGnd

Input =4.5V-7.5V

Vin

PVin

1.0uF

2.2uF

Figure 11 Single-Rail Configuration for 4.5V-7V inputs

Ext VCC

4.5V-7.5V

IR3827

VCC/

LDO_OUT

PGnd

Vin

PVin

2.2uF

Input =1.0V-21V

Figure 12 Use External Bias Voltage

SOFT-START

The IR3827 has an internal digital soft-start circuit to

control the output voltage rise time, and to limit the

current surge at the start-up. To ensure correct start-

up, the soft-start sequence initiates when the Enable

and Vcc voltages rise above their UVLO thresholds

and generate the Power On Ready (POR) signal.

The slew rate of the internal soft-start can be

adjusted externally with SS_Select pin, as shown in

Table 3.

Table 3 User Selectable Soft-Start Time

SS_Select

Slew Rate

(mV/ µs)

Soft-Start Time

( ms )

Vcc

0.4

1.5

Float

0.2

Gnd

0.1

Figure 13 shows the waveforms during the soft start.

The corresponding soft-start time can be calculated

as follows.

SlewRate

−

It should be noted that during the soft-start the over-

current protection (OCP) and over-voltage protection

(OVP) is enabled to protect the device for any short

circuit or over voltage condition.

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