SL40307A-R19KHF datasheet(23/53 Pages) IRF

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IR3846

23 www.irf.com

August 01, 2013

Figure 15: Timing Diagram for Feed-Forward (F.F.)

Function

SMART LOW DROPOUT REGULATOR (LDO)

IR3846 has an integrated low dropout (LDO) regulator

which can provide gate drive voltage for both drivers.

In order to improve overall efficiency over the whole

load range, LDO voltage is set to 6.8V (typ.) at mid- or

heavy load condition to reduce Rds(on) and thus

MOSFET conduction loss; and it is reduced to 4.4V

(typ.) at light load condition to reduce gate drive loss.

The smart LDO selects its output voltage according to

the load condition by sensing the inductor current (IL).

At light load condition, the inductor current can fall

below zero as shown in Figure 16. A zero crossing

comparator is used to detect when the inductor

current falls below zero at the LDrv Falling Edge. If the

comparator detects zero crossing events for 256

consecutive switching cycles, the smart LDO reduces

its output to 4.4V. The LDO voltage will remain low

until a zero crossing is not detected. Once a zero

crossing is not detected, the counter is reset and LDO

voltage returns to 6.8V. Figure 16 shows the timing

diagram. Whenever the device turns on, LDO always

starts with 6.8V, then goes to 4.4V / 6.8V depending

upon the load condition.

However, if only Vin is

applied with Enable low, the LDO output is 4.4V.

Figure 16: Time Diagram for Smart LDO

Users can configure the IR3846 to use a single supply

or dual supplies. Depending on the configuration used

the PVin, Vin and VCC pins are connected differently.

Below several configurations are shown.

In an

internally biased configuration, the LDO draws from

the Vin pin and provides a gate drive voltage, as

shown in Figure 17. By connecting Vin and PVin

together as shown in the Figure 18, IR3846 is an

internally biased single supply configuration that runs

off a single supply.

IR3846 can also use an external bias to provide gate

drive voltage for the drivers instead of the internal

LDO. To use an external bias, connected Vin and

VCC to the external bias. PVin can use a separate rail

as shown in Figure 19 or run off the same rail as Vin

and VCC.

Figure 17: Internally Biased Configuration

Figure 18: Internally Biased Single Supply

Configuration

SL40307A-R19KHF Datasheet(PDF) 23 Page - International Rectifier

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