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H5TC8G43AMR-PBA Datasheet(PDF) 17 Page - Hynix Semiconductor |
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H5TC8G43AMR-PBA Datasheet(HTML) 17 Page - Hynix Semiconductor |
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17 / 35 page ![]() Rev. 0.4 / Apr. 2013 17 Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Table 2 -Basic IDD and IDDQ Measurement Conditions Symbol DDR3L-1066 DDR3L-1333 DDR3L-1600 Unit 7-7-7 9-9-9 11-11-11 tCK 1.875 1.5 1.25 ns CL 7 9 11 nCK nRCD 79 11 nCK nRC 27 33 39 nCK nRAS 20 24 28 nCK nRP 79 11 nCK nFAW 1KB page size 20 20 24 nCK 2KB page size 27 30 32 nCK nRRD 1KB page size 4 4 5 nCK 2KB page size 6 5 6 nCK nRFC -512Mb 48 60 72 nCK nRFC-1 Gb 59 74 88 nCK nRFC- 2 Gb 86 107 128 nCK nRFC- 4 Gb 139 174 208 nCK nRFC- 8 Gb 187 234 280 nCK Symbol Description IDD0 Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3. IDD1 Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4. |
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