AD9226ARSZ datasheet(19/28 Pages) AD

19 / 28 page

REV. B

AD9226

–19–

MODE CONTROLS

Clock Stabilizer

The clock stabilizer is a circuit that desensitizes the ADC from

clock duty cycle variations. The AD9226 eases system clock

constraints by incorporating a circuit that restores the internal duty

cycle to 50%, independent of the input duty cycle. Low jitter on

the rising edge (sampling edge) of the clock is preserved while

the noncritical falling edge is generated on-chip.

It may be desirable to disable the clock stabilizer, and may be

necessary when the clock frequency speed is varied or completely

stopped. Once the clock frequency is changed, over 100 clock

cycles may be required for the clock stabilizer to settle to a dif-

ferent speed. When the stabilizer is disabled, the internal switching

will be directly affected by the clock state. If the external clock is

high, the SHA will be in hold. If the clock pulse is low, the SHA

will be in track. TPC 16 shows the benefits of using the clock

stabilizer. See Tables I and III.

Data Format Select (DFS)

The AD9226 may be set for binary or two’s complement data

output formats. See Tables I and II.

SSOP Package

The SSOP mode control (Pin 22) has two functions. It enables/

disables the clock stabilizer and determines the output data format.

The exact functions of the mode pin are outlined in Table I.

Table I. Mode Select (SSOP)

Mode

DFS

Clock Duty Cycle Shaping

DNC

Binary

Clock Stabilizer Disabled

AVDD

Binary

Clock Stabilizer Enabled

GND

Two’s Complement

Clock Stabilizer Enabled

10 k

Ω

Two’s Complement

Clock Stabilizer Disabled

Resistor

To GND

LQFP Package

Pin 35 of the LQFP package determines the output data format

(DFS). If it is connected to AVSS, the output word will be straight

binary. If it is connected to AVDD, the output data format will

be two’s complement. See Table II.

Pin 43 of the LQFP package controls the clock stabilizer function

of the AD9226. If the pin is connected to AVSS, both clock

edges will be used in the conversion architecture. When Pin 43

is connected to AVDD, the internal duty cycle will be determined

by the clock stabilizer function within the ADC. See Table III.

Table II. DFS Pin Controls

DFS Function

Pin 35 Connection

Straight Binary

AVSS

Two’s Complement

AVDD

Table III. Clock Stabilizer Pin

Clock Restore Function

Pin 43 Connection

Clock Stabilizer Enabled

AVDD

Clock Stabilizer Disabled

AVSS

DIGITAL INPUTS AND OUTPUTS

Digital Outputs

Table IV details the relationship among the ADC input, OTR, and

straight binary output.

Table IV. Output Data Format

Two’s

Binary

Complement

Input (V)

Condition (V)

Output Mode

Mode

OTR

VINA–VINB < – VREF

0000 0000 0000

1000 0000 0000

VINA–VINB = – VREF

0000 0000 0000

1000 0000 0000

VINA–VINB = 0

1000 0000 0000

0000 0000 0000

VINA–VINB = + VREF – 1 LSB 1111 1111 1111

0111 1111 1111

VINA–VINB

≥ + VREF

1111 1111 1111

0111 1111 1111

Out of Range (OTR)

An out-of-range condition exists when the analog input voltage

is beyond the input range of the converter. OTR is a digital

output that is updated along with the data output corresponding

to the particular sampled analog input voltage. Hence, OTR has

the same pipeline delay (latency) as the digital data. It is LOW

when the analog input voltage is within the analog input range.

It is HIGH when the analog input voltage exceeds the input

range as shown in Figure 14. OTR will remain HIGH until the

analog input returns within the input range and another conversion

is completed. By logical ANDing OTR with the MSB and its

complement, overrange high or underrange low conditions can be

detected. Table V is a truth table for the over/underrange

circuit in Figure 15, which uses NAND gates. Systems requiring

programmable gain conditioning of the AD9226 input signal

can immediately detect an out-of-range condition, thus elimi-

nating gain selection iterations. Also, OTR can be used for

digital offset and gain calibration.

Table V. Out-of-Range Truth Table

OTR

MSB

Analog Input Is

In Range

Underrange

Overrange

1111 1111 1111

1111 1111 1110

OTR

–FS

+FS

–FS +1/2 LSB

+FS – 1/2 LSB

–FS – 1/2 LSB

+FS – 1 1/2 LSB

0000 0000 0001

0000 0000 0000

OTR DATA OUTPUTS

Figure 14. OTR Relation to Input Voltage and Output Data

OVER = 1

UNDER = 1

MSB

OTR

MSB

Figure 15. Overrange or Underrange Logic

AD9226ARSZ Datasheet(PDF) 19 Page - Analog Devices

AD9226ARSZ Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL