8

Notes:

1. The module signal grounds are isolated from the module case.

2. This is an open collector/drain output that on the host board requires a 4.7 kΩ to 10 kΩ pullup resistor to VccHost. See Figure 2.

3. This input is internally biased high with a 4.7 kΩ to 10 kΩ pullup resistor to VccT.

4. Two-Wire Serial interface clock and data lines require an external pullup resistor dependent on the capacitance load.

5. This is a ground return that on the host board requires a 4.7 kΩ to 10 kΩ pullup resistor to VccHost.

Table 2. Contact Description

Contact

Symbol

Function/Description

Notes

1

VeeT

Transmitter Signal Ground

Note 1

2

TX_FAULT

Transmitter Fault (LVTTL-O) – High indicates a fault condition

Note 2

3

TX_DISABLE

Transmitter Disable (LVTTL-I) – High or open disables the transmitter

Note 3

4

SDA

Two Wire Serial Interface Data Line (LVCMOS – I/O)

(same as MOD-DEF2 in INF-8074)

Note 4

5

SCL

Two Wire Serial Interface Clock Line (LVCMOS – I/O)

(same as MOD-DEF1 in INF-8074)

Note 4

6

MOD_ABS

Module Absent (Output), connected to VeeT or VeeR in the module

Note 5

7

RS0

Rate Select 0 - Not used, Presents high input impedance.

8

RX_LOS

Receiver Loss of Signal (LVTTL-O)

Note 2

9

RS1

Rate Select 1 - Not used, Presents high input impedance.

10

VeeR

Receiver Signal Ground

Note 1

11

VeeR

Receiver Signal Ground

Note 1

12

RD-

Receiver Data Out Inverted (CML-O)

13

RD+

Receiver Data Out (CML-O)

14

VeeR

Receiver Signal Ground

15

VccR

Receiver Power + 3.3 V

16

VccT

Transmitter Power + 3.3 V

17

VeeT

Transmitter Signal Ground

Note 1

18

TD+

Transmitter Data In (CML-I)

19

TD-

Transmitter Data In Inverted (CML-I)

20

VeeT

Transmitter Signal Ground

Note 1

Figure 3. Module edge connector contacts

TOP VIEW

OF BOARD

11

20

10

1

TOWARD

HOST

BOTTOM OF

BOARD AS

VIEWED FROM

TOP THROUGH

BOARD