PIC18F1220ESLASHPQTP datasheet(119/308 Pages) MICROCHIP

119 / 308 page

DS39605F-page 117

PIC18F1220/1320

15.3.4

CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off or the CCP module is not in Capture mode,

the prescaler counter is cleared. This means that any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared; therefore, the first capture may be from

non-zero

prescaler.

Example 15-1

shows

the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 15-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

FIGURE 15-1:

CAPTURE MODE OPERATION BLOCK DIAGRAM

15.4

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against either the TMR1 register

pair value, or the TMR3 register pair value. When a

match occurs, the RB3/CCP1/P1A pin:

• Is driven high

•Is driven low

• Toggles output (high-to-low or low-to-high)

• Remains unchanged (interrupt only)

The action on the pin is based on the value of control

bits, CCP1M3:CCP1M0. At the same time, interrupt

flag bit, CCP1IF, is set.

15.4.1

CCP PIN CONFIGURATION

The user must configure the RB3/CCP1/P1A pin as an

output by clearing the TRISB<3> bit.

15.4.2

TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode

or Synchronized Counter mode if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

15.4.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen, the RB3/

CCP1/P1A pin is not affected. CCP1IF is set and an

interrupt is generated (if enabled).

15.4.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The special event trigger also sets the GO/DONE bit

(ADCON0<1>). This starts a conversion of the

currently selected A/D channel if the A/D is on.

CLRF

CCP1CON

; Turn CCP module off

MOVLW

NEW_CAPT_PS

; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF

CCP1CON

; Load CCP1CON with

; this value

CCPR1H

CCPR1L

TMR1H

TMR1L

Set Flag bit CCP1IF

TMR3

Enable

Q’s

CCP1CON<3:0>

CCP1 pin

Prescaler

÷ 1, 4, 16

and

Edge Detect

TMR3H

TMR3L

TMR1

Enable

T3CCP1

Note:

Clearing the CCP1CON register will force

the RB3/CCP1/P1A compare output latch

to the default low level. This is not the

PORTB I/O data latch.

PIC18F1220E/PQTP Datasheet(PDF) 119 Page - Microchip Technology

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