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PIC18F2610E/SOSQTP Datasheet(PDF) 228 Page - Microchip Technology |
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PIC18F2610E/SOSQTP Datasheet(HTML) 228 Page - Microchip Technology |
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228 / 376 page ![]() PIC18F2X1X/4X1X DS39636D-page 230 © 2009 Microchip Technology Inc. FIGURE 20-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 20.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 20-1) keep CVREF from approaching the refer- ence source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 25.0 “Electrical Characteristics”. 20.3 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 20.4 Effects of a Reset A device Reset disables the voltage reference by clearing bit CVREN (CVRCON<7>). This Reset also disconnects the reference from the RA2 pin by clearing bit CVROE (CVRCON<6>) and selects the high-voltage range by clearing bit CVRR (CVRCON<5>). The CVR value select bits are also cleared. 20.5 Connection Considerations The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the CVROE bit is set. Enabling the voltage reference out- put onto RA2 when it is configured as a digital input will increase current consumption. Connecting RA2 as a digital output with CVRSS enabled will also increase current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 20-2 shows an example buffering technique. CVR3:CVR0 8R R CVREN CVRSS = 0 VDD VREF+ CVRSS = 1 8R CVRSS = 0 VREF- CVRSS = 1 R R R R R R 16 Steps CVRR CVREF |
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