PIC18F2610ESLASHSOSQTP datasheet(251/376 Pages) MICROCHIP

251 / 376 page

DS39636D-page 253

PIC18F2X1X/4X1X

22.5

Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other

PIC® devices.

The user program memory is divided into five blocks.

One of these is a boot block of 2 Kbytes. The remainder

of the memory is divided into four blocks on binary

boundaries.

Each of the five blocks has three code protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 22-5 shows the program memory organization

for 16- and 32-Kbyte devices and the specific code

protection bit associated with each block.

Figure 22-6 shows the program memory organization

for 48 and 64-Kbyte devices and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 22-3.

FIGURE 22-5:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2410/2510/4410/4510

MEMORY SIZE/DEVICE

Block Code Protection

Controlled By:

16 Kbytes

(PIC18F2410/4410)

32 Kbytes

(PIC18F2510/4510)

Address

Range

Boot Block

000000h

0007FFh

CPB, WRTB, EBTRB

Block 0

000800h

001FFFh

CP0, WRT0, EBTR0

Block 1

002000h

003FFFh

CP1, WRT1, EBTR1

Unimplemented

Read ‘0’s

Block 2

004000h

005FFFh

CP2, WRT2, EBTR2

Block 3

006000h

007FFFh

CP3, WRT3, EBTR3

Unimplemented

Read ‘0’s

1FFFFFh

(Unimplemented Memory Space)

PIC18F2610E/SOSQTP Datasheet(PDF) 251 Page - Microchip Technology

PIC18F2610E/SOSQTP Datasheet(HTML) 251 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL