PIC18F2610ESLASHSOSQTP datasheet(252/376 Pages) MICROCHIP

252 / 376 page

PIC18F2X1X/4X1X

DS39636D-page 254

FIGURE 22-6:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2515/2610/4515/4610

TABLE 22-3:

SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

—

—CP3(1,2)

CP2(1)

CP1

CP0

300009h

CONFIG5H

—CPB

—

30000Ah

CONFIG6L

—

—WRT3(1,2)

WRT2(1)

WRT1

WRT0

30000Bh

CONFIG6H

—

WRTB

WRTC

—

30000Ch

CONFIG7L

—

—EBTR3(1,2)

EBTR2(1)

EBTR1

EBTR0

30000Dh

CONFIG7H

—EBTRB

—

Legend:

Shaded cells are unimplemented.

Note 1:

Unimplemented in PIC18F2410/4410 devices; maintain this bit set.

Unimplemented in PIC18F2515/4515 devices; maintain this bit set.

MEMORY SIZE/DEVICE

Block Code Protection

Controlled By:

48 Kbytes

(PIC18F2515/4515)

64 Kbytes

(PIC18F2610/4610)

Address

Range

Boot Block

000000h

0007FFh

CPB, WRTB, EBTRB

Block 0

000800h

003FFFh

CP0, WRT0, EBTR0

Block 1

004000h

007FFFh

CP1, WRT1, EBTR1

Block 2

008000h

00BFFFh

CP2, WRT2, EBTR2

Unimplemented

Read ‘0’s

Block 3

00C000h

00FFFFh

CP3, WRT3, EBTR3

Unimplemented

Read ‘0’s

010000h

1FFFFFh

(Unimplemented Memory Space)

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