CDCLVD110AVF datasheet(5/18 Pages) TI

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CDCLVD110A

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SCAS841C – FEBRUARY 2007 – REVISED NOVEMBER 2009

LVDS — SWITCHING CHARACTERISTICS

over recommended operating free-air temperature range, VDD = 2.5 V ±5%

FROM

PARAMETER

MIN

TYP

MAX

UNIT

(INPUT)

(OUTPUT)

CLK0, CLK0

tPLH

Propagation delay low-to-high

Qn, Qn

CLK1, CLK1

Propagation delay high-to-low

CLK0, CLK0

tPHL

Qn, Qn

CLK1, CLK1

CLK0, CLK0

tduty

Duty cycle

Qn, Qn

45%

55%

CLK1, CLK1

tsk(o)

Output skew

Any Qn, Qn

tsk(p)

Pulse skew

Any Qn, Qn

tsk(pp)

Part-to-part skew

Any Qn, Qn

600

Output rise time, 20% to 80%, RL = 100 Ω, CL = 5 pF

Any Qn, Qn

350

Output fall time, 20% to 80%, RL = 100 Ω, CL = 5 pF

Any Qn, Qn

350

CLK0, CLK0

fclk

Max input frequency

Any Qn, Qn

900

1100

MHz

CLK1, CLK1

CONTROL REGISTER CHARACTERISTICS

over recommended operating free-air temperature range, VDD = 2.5 V ±5% (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fMAX

Maximum frequency of shift register

100

150

MHz

tsu

Setup time, clock to SI

Hold time, clock to SI

1.5

tremoval

Removal time, enable to clock

1.5

tstartup

Startup time after disable through SI

1.0

μs

Clock pulse width, minimum

VIH

Logic input high

VDD = 2.5 V

VIL

Logic input low

VDD = 2.5 V

0.8

Input current, CK pin

–5

IIH

VI = VDD

μA

Input current, SI and EN pins

–30

Input current, CK pin

–10

IIL

VI = GND

μA

Input current, SI and EN pins

–5

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